LAN7430 datasheet(33/77 Pages) MICROCHIP

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DS00002631D-page 33

LAN7430/LAN7431

6.3

Gigabit Ethernet Media Access Controller (MAC)

The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ether-

net/IEEE 802.3-compliant node and interfaces to the integrated Gigabit Ethernet PHY (LAN7430 only), or MII/RGMII

interface (LAN7431 only). The MAC can operate in full-duplex 1000 Mbps or half/full-duplex 10/100 Mbps mode.

When operating in half-duplex mode, the MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard)

and ANSI/IEEE 802.3 standards. When operating in full-duplex mode, the MAC complies with IEEE 802.3x full-duplex

operation standard.

The MAC provides programmable enhanced features designed to minimize Host supervision, bus utilization, and pre-

or post-message processing. These features include the ability to disable retries after a collision, dynamic FCS (Frame

Check Sequence) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum

frame size attributes, and automatic retransmission and detection of collision frames.

The primary attributes of the MAC are:

• Interfaces to the internal Gigabit Ethernet PHY (LAN7430 only), or MII/RGMII interface (LAN7431 only)

• Transmit and receive message data encapsulation

• Framing (frame boundary delimitation, frame synchronization)

• Error detection (physical medium transmission errors)

- Including Length Field testing

• FCS checking/stripping/generation

• Preamble stripping/generation

• Media access management

• Medium allocation (collision detection, except in full-duplex operation)

• Contention resolution (collision handling, except in full-duplex operation)

• Flow control during full-duplex mode

• Decoding of control frames (PAUSE command) and disabling the transmitter

• Generation of control frames (PAUSE command)

• Maintains minimum inter packet gap (IPG)

• Magic packet/Wake-On-LAN (WOL) detection

• Remote wakeup frame detection

• Neighbor Solicitation offload

• ARP offload

• Implements Simple Network Management Protocol (SNMP) and Remote Monitoring (RMON) management

counter sets

• Jumbo frames supported up to 9220 bytes

6.4

RGMII (LAN7431 Only)

The integrated Reduced Gigabit Media Independent Interface (RGMII) is a Dual Data Rate (DDR) interface that consists

of a transmit path and a receive path. Both paths have an independent clock (TXC & RXC), 4 data signals, and a control

signal. Because of this design, RGMII does not have distinct PHY/MAC roles and special hardware considerations are

not required for a MAC-to-MAC connection. When source-synchronous clocking is used for MAC-to-MAC connections,

the clock signal that is output (by either path) is synchronous with the related data signals. This requires the PCB to be

designed to add a 1.5-2 ns delay to the clock signal to meet the setup and hold times on the sink. The RGMII interface

supports both Version 1.3 and Version 2.0 of the RGMII specification. Version 1.3 of the RGMII Specification requires a

1.5 to 2ns clock delay via a PCB trace delay. Version 2.0 of the RGMII Specification introduces the option of an on-chip

Internal Delay (ID). These distinct RGMII modes of operation are referred to as “Non-ID Mode” and “ID Mode”, respec-

tively.

The LAN7431 requires an external 125MHz clock reference on the CLK125 pin. The LAN7431 MAC may receive a 125

MHz reference clock from the partner PHY or MAC, which is used for generating the RGMII TXC signal. If this option is

not available, the Generate CLK125 MHz Enable (CLK125_EN) field of the Hardware Configuration Register

(HW_CFG) shall be set. When set, the device will generate the 125 MHz clock internally. For the processor MAC, sev-

eral options are possible:

• The 125MHz clock reference is available internally.

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