LAN7430 datasheet(35/77 Pages) MICROCHIP

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DS00002631D-page 35

LAN7430/LAN7431

6.5

Gigabit Ethernet PHY (GPHY) (LAN7430 Only)

The device (LAN7430 only) incorporates a low-power Gigabit Ethernet PHY (GPHY) transceiver that is fully compliant

with the IEEE 802.3, 802.3u, 802.3ab, and 802.3az (Energy Efficient Ethernet) standards. It provides a low electromag-

netic interference (EMI) line driver, and integrated line side termination resistors that conserve both power and printed

circuit board (PCB) space.

The mixed signal and digital signal processing (DSP) architecture of the Ethernet PHY assures robust performance

even under less-than-favorable environmental conditions. It supports both half-duplex and full-duplex 10BASE-T and

100BASE-TX, and full-duplex 1000BASE-T communication speeds over Category 5 (Cat5) unshielded twisted pair

(UTP) cable at distances greater than 100m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of

ambient environment and system electronic noise. The Ethernet PHY implements Auto-Negotiation to automatically

determine the best possible speed and duplex mode of operation. Auto-MDIX support allows the use of direct connect

or cross-over LAN cables.

The Ethernet PHY is configurable via the Ethernet PHY Control and Status. These registers are accessed indirectly

through the Ethernet MAC via the MII Access Register (MII_ACCESS) and MII Data Register (MII_DATA).

The Gigabit Ethernet PHY has the following main features:

• Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100/1000 Mbps) and Duplex (Half/Full)

• Voltage-mode Line driver with On-Chip Termination Resistors for the Differential Pairs

• Jumbo Frame Support Up to 16 KB (MAC supports 9220 bytes)

• Energy-Detect Power-Down Mode for Reduced Power Consumption When the Cable is not attached

• Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/

1000BASE-T and Transmit Amplitude Reduction with 10BASE-Te Option

• Programmable LED Outputs for Link, Activity, and Speed

• Baseline Wander Correction

• TDR-based Cable Diagnostic to Identify Faulty Copper Cabling

• Loopback Modes for Diagnostics

• Automatic MDI/MDI-X Crossover to Detect and Correct Pair Swap at All Speeds of Operation

• Automatic Detection and Correction of Pair Swaps, Pair Skew, and Pair Polarity

• Power-Down and Power-Saving Modes

• Signal Quality Indication

6.6

IEEE 1588v2 (PTP)

The device provides hardware support for the IEEE 1588-2008 (v2) Precision Time Protocol (PTP), allowing clock syn-

chronization with remote Ethernet devices, packet time stamping, and time driven event generation.

The device may function as a master or a slave clock per the IEEE 1588-2008 specification. End-to-end and peer-to-

peer link delay mechanisms are supported as are one-step and two-step operations.

A 32-bit seconds and 30-bit nanoseconds tunable clock is provided that is used as the time source for all PTP timestamp

related functions. A 1588 Clock Events sub-module provides 1588 Clock comparison based interrupt generation and

timestamp related GPIO event generation. GPIO pins can be used to trigger a timestamp capture when configured as

an input, or output a signal based on a 1588 Clock timer compare event.

All features of the IEEE 1588 unit can be monitored and configured via their respective configuration and status regis-

ters.

6.6.1

IEEE 1588-2008

IEEE 1588-2008 specifies a Precision Time Protocol (PTP) used by master and slave clock devices to pass time infor-

mation in order to achieve clock synchronization. Ten network message types are defined:

• Sync

• Follow_Up

• Delay_Req

• Delay_Resp

• PDelay_Req

• PDelay_Resp

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