LAN7430 datasheet(41/77 Pages) MICROCHIP

41 / 77 page

 2018-2019 Microchip Technology Inc.

DS00002631D-page 41

LAN7430/LAN7431

• The device’s non-PCIe functionality is reset.

• The FLR routine exits.

6.12.6

SOFT RESET

This is a software issued reset when the Soft Reset (SRST) bit in the Hardware Configuration Register (HW_CFG) is

set. It is used to completely reset the device as if it was a cold reset.

As with a POR and RESET_N:

• The entire device is reset.

• A timer within the device will assert the internal reset for approximately 20 ms.

• The EEPROM/OTP contents are loaded by this reset.

6.12.7

SOFT-LITE RESET

This is a software issued reset when the Soft Lite Reset (LRST) bit in the Hardware Configuration Register (HW_CFG)

is set. It is used to reset only the device function without resetting the PCIe portion.

6.12.8

POWER MANAGEMENT SOFT RESET

This reset is created when the device’s power state is changed from D3hot to D0u by writing a 00b to the PowerState

field in the Power Management Control/Status PCIe configuration register while the No_Soft_Reset field is clear.

6.12.9

ETHERNET PHY SOFTWARE RESET

The Ethernet PHY software reset is triggered via the Ethernet PHY Reset (ETH_PHY_RST) bit in the Power Manage-

ment Control Register (PMT_CTL). It holds the Ethernet PHY reset for a minimum of 2 ms.

For the LAN7431 (external Ethernet PHY), the PHY_RESET_N pin is asserted during this reset. The Device Ready

(READY) bit in the Power Management Control Register (PMT_CTL) asserts after the 2 ms PHY_RESET_N assertion

interval completes. An optional 125ms delay can be enabled to allow for the external PHY to become ready. This is

enabled with the External PHY Ready Delay Enable (EXT_PHY_RDY_EN) bit.

For the LAN7430 (internal Ethernet PHY), the Device Ready (READY) asserts when the internal PHY is functional, fol-

lowing the reset.

6.12.10

EXTERNAL PHY RESET

The LAN7431 uses the dedicated PHY_RESET_N pin for automatically resetting the external Ethernet PHY. This pin

automatically asserts as part of the reset sequence. The PHY_RESET_N may also be asserted by an Ethernet PHY

Software Reset.

Note:

This reset will cause a detach from the PCIe bus, which may cause host software issues if unexpected.

Note:

Software must stop all RX and TX channels of the DMA controller before setting this bit.



Software must disable all interrupts before setting this bit.



Software must not access any device Control and Status Registers (PCIe Configuration Space registers

excluded) for at least 5µS after setting Soft Lite Reset (LRST).



Software should verify that Soft Lite Reset (LRST) has self-cleared before performing any device opera-

tions or setting any device CSRs (PCIe Configuration Space registers excluded)

APPLICATION NOTE:

Although some registers are returned to their last EEPROM or OTP specified default upon

a Soft Like Reset (LRST), the device does not automatically reload its full configuration

(including the User Initialization Table) from OTP or EEPROM. If necessary or desired,

software may issue a Host Initiated EEPROM or OTP Reload.

Note:

The Ethernet PHY Software Reset is not a chip-level reset. It resets only the Ethernet PHY.

LAN7430 датащи(PDF) 41 Page - Microchip Technology

LAN7430 датащи(HTML) 41 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

датащи скачать

ссылки URL