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LAN7430 датащи(PDF) 62 Page - Microchip Technology |
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LAN7430 датащи(HTML) 62 Page - Microchip Technology |
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62 / 77 page ![]() LAN7430/LAN7431 DS00002631D-page 62 2018-2019 Microchip Technology Inc. 7.6.6.2 RGMII Transmit Timing (TXC Internal Delay Disabled - PCB Provides Delayed Clock) Note 7-25 7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation. Minimum limits are non-sustainable long term. Note 7-26 8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation. Note 7-27 8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation. Maximum limits are non-sustainable long term. Note 7-28 45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation. Note 7-29 55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation. FIGURE 7-9: RGMII TRANSMIT TIMING (TXC INTERNAL DELAY DISABLED) TABLE 7-17: RGMII TRANSMIT TIMING VALUES (TXC INTERNAL DELAY DISABLED) Symbol Description Min Typ Max Units ttxc TXC period Note 7-25 Note 7-26 Note 7-27 ns tclkh TXC high time Note 7-28 50 Note 7-29 % tclkl TXC low time Note 7-28 50 Note 7-29 % tskew Data to clock output skew (at transmitter output) -400 400 ps TXC TXD[3:0] TX_CTL tclkh tclkl ttxc TXD [3:0] TXD [7:4] TXEN TXER tskew tskew tskew tskew |
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