89 / 129 page  Port Definitions 84 PRELIMINARY V1.8 Figure 28. Port 4 Address C0H Bit Addr. C7H C6H C5H C4H C3H C2H C1H C0H BIT 7 6 5 4 3 2 1 0 NAME P47 P46 P45 P44 P43 P42 P41 P40 Definition Port-4 Pin or Latch bit-7 Port-4 Pin or Latch bit-6 Port-4 Pin or Latch bit-5 Port-4 Pin or Latch bit-4 Port-4 Pin or Latch bit-3 Port-4 Pin or Latch bit-2 Port-4 Pin or Latch bit-1 Port-4 Pin or Latch bit-0 Reset Value 0 0 0 0 0 0 0 0 Read/Write by Software R/W P4latin=1: P47 Latch Read P4latin=0: P4.7 Pin Read R/W P4latin=1: P46 Latch Read P4latin=0: P4.6 Pin Read R/W P4latin=1: P45 Latch Read P4latin=0: P4.5 Pin Read R/W P4latin=1: P44Latch Read P4latin=0: P4.4 Pin Read R/W P4latin=1: P43 Latch Read P4latin=0: P4.3 Pin Read R/W P4latin=1: P42 Latch Read P4latin=0: P4.2 Pin Read R/W P4latin=1: P41 Latch Read P4latin=0: P4.1 Pin Read R/W P4latin=1: P40 Latch Read P4latin=0: P4.0 Pin Read MUX 0 1 SFR P4 [7:0] Pin SFR P4RD [7:0] To CPU R PMOS VDD or NHIZ SFR P4IO [7:0] P4LATIN MUX 0 1 RFPWROE, PLLSWOE RFPWR PLLSW |
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