Special function registers
8
PRELIMINARY V1.8
The SFR register definitions are described within each peripheral block description and
the general CPU registers SP, DPTR, PSW, ACC, B, and MSIZ are described below.
The underlined names are the registers for the CPU and the dashed lines are for registers
used in standard 8051 devices but not used by the SS1102C microcontroller.
7.1.
Stack Pointer (SP)
The SP register contains the stack pointer. The stack pointer is used to load the program
counter into memory during LCALL and ACALL instructions, and is used to retrieve
the program counter from memory in RET and RETI instructions. The stack may also
be saved or loaded using PUSH and POP instructions, which also increment and
decrement the stack pointer. The stack pointer points to the top location of the stack. On
reset the stack pointer is set to 07 hex.
7.2.
Data Pointer (DPTR)
The Data Pointer (DPTR) is 16 bits in size, and consists of two registers, the Data
Pointer High byte (DPH), and the Data Pointer Low byte (DPL). Two 16 bit operations
are possible on this register, they are load immediate and increment. This register is
used for 16 bit address external memory accesses, for offset code byte fetches, and for
offset program jumps. On reset the value of this register is 0000 hex.
7.3.
Program Status Word (PSW)
This register contains status information resulting from CPU and ALU operation. The
bit definitions are given below:
• PSW.7 CY. ALU carry flag.
• PSW.6 AC. ALU auxiliary carry flag.
• PSW.5 F0. General purpose user definable flag.
• PSW.4 RS1. Register bank select bit 1.
• PSW.3 RS0. Register bank select bit 0.
• PSW.2 OV. ALU overflow flag.
• PSW.1 F1. User definable flag.
• PSW.0 P. Parity flag. Set each instruction cycle to indicate odd/even parity in the
accumulator.
On reset this register returns 00 hex.
The register bank select bits operate as follows
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