SPI (Serial Peripheral Interface)
30
PRELIMINARY V1.8
If the WD Reset is enabled and a WD underflow happens, the MCU goes into Reset
state and all registers are initialized again. The Program Counter will point to the
address 0000H. The software initialization routine can check the WDRST bit to
distinguish the reset source.
In any case, the WDINT bit is set to high when the underflow happens. If the WD-
Timer interrupt is enabled by the Interrupt Control Block, the interrupt service routine
for the WD-Timer will be served. At this time the WDINT bit will be cleared by
hardware.
Note: Writing “FFh” to the down counter register while it is in the “00h” state, might
cause the “Underflow”. Writing anything other than “FFh” will not cause the
“Underflow”.
11. SPI (Serial Peripheral Interface)
11.1.
Overview
The SS1102C includes an 8-bit SPI which allows to communicate with peripheral or
microcontroller devices equipped with a compatible SPI function. The SPI supports
full-duplex communications by allowing 8-bit of data to be synchronously transmitted
and received. An SPI system should contain one master device and several slave
devices.
The SS1102C can only be configured as an SPI master.
11.2.
SPI Pin and Timing Description
Basically, three pins (MI, MO, SCK) are used to accomplish the communication:
• Master In (MI): MI is configured as a data input. The most significant data bit is
receive first.
• Master Out (MO): MO is configured as a data output. The most significant data bit is
sent first.
• Serial Clock (SCK): The master clock used to synchronize data transfer through MI
and MO. Since SCK is generated by the master device, this pin is configured as an
output.
11.3.
SPI Timing Description
As shown in Fig. 1, four possible timing relationships may be chosen by using control
bits CPOL (clock polarity) and CPHA (clock phase) in the serial peripheral control
register(SPI1CR). Both master and slave device must operate with the same timing.
The clock frequency is selected by using control bits SPR0 and SPR1 in the SPI1CR of
the master device. The slave device has no control of the clock frequency.
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
