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SPI (Serial Peripheral Interface)
PRELIMINARY V1.8
35
TABLE 27.
Description of SPI Status Register (SPI1SR)
11.7.
SPI Shift Register (SPIDAT)
TABLE 28.
Definition of SPIDAT
Name
Bit
Description
SPIF
7
SPIF: SPI Transfer Complete Flag
0: Data transfer not complete
1: Data transfer complete
If SPIF goes high and if SPIE is set, an internal interrupt is generated. SPIF can be cleared
by reading SPI1SR followed by an read of the SPI1DAT. A write to SPI1DAT will be
ignored if SPIF is set.
WCOL
6
WCOL: SPI Write Collision Detect
0: No collision
1: Collision: Attempt to write to SPI1DAT while data transfer is still in progress.
When CPHA is low, a transfer starts when SS (Slave Select in slave device) goes low and
finishes when SS (Slave Select in slave device) goes high.
When CPHA is high, a transfer starts when SCK first becomes active while SS (Slave
Select in slave device) is low. The transfer finishes when SPIF is set.
WCOL can be cleared by reading SPI1SR followed by a read of the SPI1DAT.
Reserved [5:0]
5-0
Address
F2H
Bit Addr. None
BIT
7
6
5
4
3
2
1
0
NAME
SPIDAT[7:0]
Definition
Reset
Value
0
0
0
0
0
0
0
0
Read/
Write by
Software
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Write by
Hardware
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
Written with
a new shift
value
0 or 1.
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