79 / 129 page  Port Definitions 74 PRELIMINARY V1.8 Figure 26. PORT-2 Address A0H Bit Addr. A7H A6H A5H A4H A3H A2H A1H A0H BIT 7 6 5 4 3 2 1 0 NAME P27 P26 P25 P24 P23 P22 P21 P20 Definition Port-2 Pin or Latch bit-7 Port-2 Pin or Latch bit-6 Port-2 Pin or Latch bit-5 Port-2 Pin or Latch bit-4 Port-2 Pin or Latch bit-3 Port-2 Pin or Latch bit-2 Port-2 Pin or Latch bit-1 Port-2 Pin or Latch bit-0 Reset Value 1 1 1 1 1 1 1 1 Read/Write by Software R/W RMW Ins: P27 Latch Read Other Ins: P2.7 Pin Read R/W RMW Ins: P26 Latch Read Other Ins: P2.6 Pin Read R/W RMW Ins: P25 Latch Read Other Ins: P2.5 Pin Read R/W RMW Ins: P24 Latch Read Other Ins: P2.4 Pin Read R/W RMW Ins: P23 Latch Read Other Ins: P2.3 Pin Read R/W RMW Ins: P22 Latch Read Other Ins: P2.2 Pin Read R/W RMW Ins: P21 Latch Read Other Ins: P2.1 Pin Read R/W RMW Ins: P20 Latch Read Other Ins: P2.0 Pin Read MUX 0 1 SFR P2 [7:0] Pin SFR P2RD [7:0] To CPU MUX Read-Modify-Write ADDR R PMOS VDD or Output Enable NHIZ |
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