SS1102C datasheet(46/129 Pages) ETC1

46 / 129 page

Direct Sequence Spread Spectrum Baseband Modem (SSTM)

PRELIMINARY V1.8

Figure 14.

Receiver Lock State Machine

If the state machine is turned on, then the receiver will not declare LOCK loss right after

UW has not been detected. Instead, it will allow for UW errors in up to two further

bursts before declaration LOCK loss. The state diagram for this lock state machine is

shown in Figure 14. In the figure, UW4DET indicates the condition when the four UWs

have been detected during acquisition burst, UWDET indicate the condition where the

single UW in empty and data bursts has been detected. M_SB is the programmed bit

(CI_h[0]) which is a binary “1” when the SSTM is programmed to be the master and a

binary “0” when programmed as a slave. NMODE is a signal generated by the receive

logic when the digital phase locked loop in the receiver has achieved lock, it is similar

to an RSSI signal. Note that the NMODE signal is independent of the UW detection.

Physically, when NMODE is asserted, it indicates that PN acquisition has been

achieved. The LOCKED and RLOCK states are as described previously.

12.8.

System Delay

To calculate the delay through the system (see Figure 15.), assume that the transmit

FIFO is almost empty at the end of a burst. Then the next bit that enters the transmit

FIFO will experience a system delay (excluding propagation delay but including the

internal logic delay) of approximately:

(EQ 3)

where TG is the time delay due to Guard Time (note: G = G1 = G2 = 28bits), TPR is the

time delay due to preamble, TUW is the time delay of the UW, TSW is the time delay for

RLOCK

LOCKED

UNLOCKED

UWDET

UW4DET

UWDET

NMODE +M_SB.UW4DET

+UWDET

UWDET

RLOCK

UWDET

delay

()

DAT

T∆

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