ii
PRELIMINARY V1.8
11.2. SPI Pin and Timing Description
....................................................30
11.3. SPI Timing Description
..................................................................30
11.4. SPI Operation
.................................................................................31
11.5. SPI Control Register (SPICR)
........................................................33
11.6. SPI Status Register (SPI1SR)
........................................................34
11.7. SPI Shift Register (SPIDAT)
..........................................................35
12. Direct Sequence Spread Spectrum Baseband Modem (SSTM)
.................37
12.1. Receiver
.........................................................................................37
12.2. Transmitter
.....................................................................................37
12.3. TDD Controller
..............................................................................38
12.4. FIFOs
.............................................................................................38
12.5. Master Clock Generator
.................................................................38
12.6. Full-Duplex Operation
...................................................................38
12.7. TDD Protocol
.................................................................................39
12.8. System Delay
.................................................................................41
12.9. Timing Information
........................................................................42
12.9.1 Full Duplex Operations
.....................................................42
12.9.2 Threshold Value Calculation
.............................................43
12.10. Half-duplex Operation
.................................................................44
12.11. Reading the Signaling Word and S/N Data
..................................47
12.12. Control Registers
.........................................................................48
12.13. SSTM Control Registers
..............................................................48
12.14. Configuration Information Bits
...................................................51
12.15. RF/IF Analog Interface
................................................................52
12.16. Programming the SSTM
..............................................................54
12.17. PN Sequence and UW Selection
..................................................55
12.18. PN Sequence Selection
................................................................55
12.19. UW Selection
...............................................................................56
12.20. Generating the PN and UW sequences
........................................57
13. Power-Saving Modes
.................................................................................58
13.1. Overview
........................................................................................58
13.2. Mode Definition and Transition
.....................................................59
13.3. FastAll mode (a Clocking Mode)
..................................................60
13.4. SlowAll mode (a Clocking Mode)
.................................................60
13.5. StopAll mode (a Clocking Mode)
..................................................60
13.6. FastPeri mode (a Clocking Mode)
.................................................61
13.7. SlowPeri mode (a Clocking Mode)
...............................................61
13.8. NorPin mode (a Pin State Mode)
...................................................61
13.9. HIZ mode (a Pin State Mode)
........................................................61
13.10. Power-Saving Control Register (PSCR)
......................................62
13.11. Stop Release Register (SREL)
.....................................................64
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