CS61310

DS440F1 FEB ‘03

23

SDO - Serial Data Output, Pin 25 (Host Mode).

Status and control information are output from the on-chip register on SDO. If CLKE is high, SDO is

valid on the rising edge of SCLK. If CLKE is low, SDO is valid on the falling edge of SCLK. SDO goes

to a high-impedance state when the serial port is being written to, or after bit D7 is output or CS goes

high (whichever occurs first).

CS - Chip Select, Pin 26 (Host Mode).

The serial interface is accessible when CS transitions from high to low.

SCLK - Serial Clock Input, Pin 27 (Host Mode).

SCLK is used to write or read data bits to or from the serial port registers.

CLKE - Clock Edge Input, Pin 28 (Host Mode).

Setting CLKE to logic 1 causes RPOS and RNEG (RDATA) to be valid on the falling edge of RCLK, and

SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and

RNEG (RDATA) to be valid on the rising edge of RCLK and SDO to be valid on the falling edge of

SCLK.

Data Input/Output

TCLK - Transmit Clock Input, Pin 2.

The 1.544 MHz transmit clock is input on this pin. TPOS and TNEG or TDATA are sampled on the

falling edge of TCLK.

TPOS/TNEG - Transmit Positive Pulse, Transmit Negative Pulse, Pins 3 and 4.

Data input to TPOS and TNEG is sampled on the falling edge of TCLK and transmitted onto the line at

TTIP and TRING. An input on TPOS results in transmission of a positive pulse; an input on TNEG

results in transmission of a negative pulse. If TNEG, pin 4, is held high for 16 TCLK cycles, the

CS61310 reconfigures for unipolar (single pin NRZ) data input at pin 3, TDATA. If TNEG goes low the

CS61310 switches back to two-pin bipolar data input format.

TDATA - Transmit Data, Pin 3.

When pin 4, TNEG/UBS, is held high, pin 3 becomes TDATA, a single-line NRZ (unipolar) data input

sampled on the falling edge of TCLK.

UBS - Unipolar / Bipolar Select, Pin 4.

When UBS is held high for 16 consecutive TCLK cycles (15 consecutive bipolar violations) the CS61310

reconfigures for unipolar (single-line NRZ) data input / output format. Pin 3 becomes TDATA, pin 7

becomes RDATA, and pin 6 becomes BPV.

NEG/RPOS - Receive Negative Pulse, Receive Positive Pulse, Pins 6 and 7.

Recovered data output on RPOS and RNEG is stable and valid on the rising edge of RCLK in Hardware

Mode. In Host Mode, CLKE determines the edge of RCLK on which RPOS and RNEG are valid. A

positive pulse on RTIP with respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING

with respect to RTIP generates a logic 1 on RNEG.

BPV - Bipolar Violation, Pin 6.

When pin 4 (TNEG/UBS) is held high, received bipolar violations are flagged by BPV (RNEG) going

high along with the offending bit output from RDATA. If the B8ZS encoder/decoder is activated, BPV will

not flag bipolar violations resulting from valid zero substitutions.