CS61310

6

DS440F1 FEB ‘03

T1 SWITCHING CHARACTERISTICS

(TA = -40

°Cto85°C; TV+, RV+ = 5.0 V ±5%;

GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)

Notes: 17. MCLK provided by an external source or TCLK.

18. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached.

19. At max load of 1.6 mA and 50 pF.

20. Host Mode (CLKE = 1).

21. Host Mode (CLKE = 0)

Parameter

Symbol

Min

Typ

Max

Units

TCLK Frequency

-

1.544

-

MHz

TCLK Duty Cycle

45

50

55

%

MCLK Frequency

(Note 17)

-

1.544

-

MHz

RCLK Duty Cycle

45

50

55

%

Rise Time, All Digital Outputs

(Note 19)

-

-

85

ns

Fall Time, All Digital Outputs

(Note 19)

-

-

85

ns

TPOS/TNEG to TCLK Falling Setup Time

25

-

-

ns

TCLK Falling to TPOS/TNEG Hold Time

25

-

-

ns

RPOS/RNEG Valid Before RCLK Falling

(Note 20)

150

274

-

ns

RPOS/RNEG Valid Before RCLK Rising

(Note 21)

150

274

-

ns

RPOS/RNEG Valid After RCLK Falling

(Note 20)

150

274

-

ns

RPOS/RNEG Valid After RCLK Rising

(Note 21)

150

274

-

ns