CS61310 datasheet(10/30 Pages) CIRRUS

10 / 30 page

CS61310

DS440F1 FEB ‘03

after 175 bit periods, preventing transmission

when data input is not present. In host mode, the

transmitter can be set to high impedance by setting

the TxHIZ bit (CR2.1) to “1.”

When any transmit control bit (TAOS, LEN0-2,

LBO1-2, or LLOOP) is toggled, the transmitter out-

puts will require approximately 22 bit periods to

stabilize. The transmitter will take longer to stabi-

lize when RLOOP is selected because the timing

circuitry must adjust to the new frequency.

2.4

Transmit All Ones Select

The transmitter provides for all ones to be generat-

ed at TTIP and TRING. The timing of the bits is

controlled by TCLK; if TCLK is absent, then MCLK

is used; in the absence of MCLK, the quartz crystal

generates the output timing. Transmit all ones is

selected in hardware mode by setting the TAOS

pin high (CR1.7 = 1 in host mode). When TAOS is

active, the TPOS and TNEG (TDATA) inputs are

ignored. If Remote Loopback is in effect, any

TAOS request will be ignored.

2.4.1

Receiver

A noise and cross-talk filter removes signal compo-

nents that are coupled onto the line from other ca-

bles. The clock and data recovery circuit exceeds

the jitter tolerance specifications of Publication

43802, Publication 43801, AT&T 62411, and

TR-TSY-000170. Jitter tolerance is shown in

Figure 7. The RTIP and RRING inputs are biased

to an intermediate DC level and treat the input sig-

nal differentially.

The receiver extracts data and clock from the input

signal. The receiver outputs are the clock and syn-

chronized data. The incoming pulses are amplified,

equalized and filtered before being fed to the com-

parator for peak detection, slicing and data recov-

ery.

2.4.2

Clock Recovery

The clock recovery circuit is a third-order phase-

locked loop. The digital PLL in the clock recovery

circuit of the CS61310 recovers clock from the

edges of the incoming pulses (1’s). The clock and

data recovery circuit is tolerant of long strings of

consecutive zeros, and will successfully receive a

1-in-175, jitter-free input signal.

In the hardware mode, data on RPOS and RNEG

(RDATA), is stable and latched on the rising edge

of recovered clock, RCLK. In host mode, the CLKE

pin determines the clock polarity for which output

data is stable and valid (see Table 2). When CLKE

is high, RPOS and RNEG (RDATA) are valid on

the falling edge of RCLK. When CLKE is low,

RPOS and RNEG are valid on the rising edge of

RCLK.

Setting TNEG high for more than 16 TCLK cycles

enables the coder mode, changing TPOS to TDA-

TA, RPOS to RDATA, and RNEG to BPV. When

configured for coder mode, the MODE pin can be

tied to RCLK enabling the B8ZS encoders and de-

coders.

2.4.3

Jitter Tolerance

The receiver jitter tolerance is shown in Figure 7.

The CS61310 jitter tolerance exceeds AT&T

62411 for synchronizers.

MODE

CLKE

DATA

CLOCK

Clock Edge for

Valid Data

LOW

Don’t

Care

RPOS

RNEG

RCLK

Rising

HIGH

LOW

RPOS

RNEG

SDO

RCLK

SCLK

Rising

Falling

HIGH

RPOS

RNEG

SDO

RCLK

SCLK

Falling

Rising

Table 2. Data Output/Clock Relationship

10 k

100

100k

700

100

300

PEAK-TO-PEAK

JITTER

(un it inte rva ls)

JITTER FREQ UENCY

(H z)

AT& T 6 2411

P erform ance

138

Min im u m

Figure 7. Minimum Input Jitter Tolerance of Receiver

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