CS61310 datasheet(16/30 Pages) CIRRUS

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CS61310

DS440F1 FEB ‘03

2.18

Power On Reset / Reset

Upon power-up, the IC is held in a static state until

the supply crosses a threshold of approximately

3 Volts. When this threshold is crossed, the device

will delay for about 10 ms to allow the power sup-

ply to reach operating voltage. After this delay, cal-

ibration of the transmit and receive sections

commences. Because power up conditions can

vary considerably, it is recommended that the de-

vice be reset after the power supply has stabilized

to ensure a known initial operational condition.

The internal frequency generators can be calibrat-

ed only if a reference clock is present. The refer-

ence clock for the transmitter is provided by TCLK.

The reference for the receiver is either the crystal

oscillator or MCLK. If both the oscillator and MCLK

are active, MCLK will be used as the reference

source. The initial calibration should take less than

20 ms after pulses are input to the receiver.

In operation, the device is continuously calibrated,

making the performance of the device independent

of power supply or temperature variations. The

continuous calibration function forgoes any re-

quirement to reset the line interface when in oper-

ation. However, a reset function is available which

will reinitiate calibration and clear all registers and

clear the Network Loopback function.

In Host Mode, a reset is initiated by simultaneously

writing RLOOP and LLOOP to the register. The re-

set will set all registers to “0” and initiate a calibra-

tion.

In Hardware Mode, the CS61310 is reset by simul-

taneously setting RLOOP and LLOOP high for at

least 200 ns. Hardware reset will clear Network

Loopback functionality

2.19

Power Supply

The device operates from a single +5 Volt supply.

Separate pins for transmit and receive supplies

provide internal isolation. These pins should de-

coupled to their respective grounds.

Decoupling and filtering of the power supplies is

crucial for the proper operation of the analog cir-

cuits in both the transmit and receive paths. A

µF tantalum and 1.0µF mylar or ceramic capac-

itor should be connected between TV+ and TGND,

anda0.1

µF mylar or ceramic capacitor should be

connected between RV+ and RGND. Place capac-

itors as closely as possible to their respective pow-

er supply pins. Wire-wrap breadboarding of the line

interface is not recommended because lead resis-

tance and inductance serve to defeat the function

of the decoupling capacitors.

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