CS61310 datasheet(9/30 Pages) CIRRUS

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CS61310

DS440F1 FEB ‘03

2. THEORY OF OPERATION

The CS61310 Line Interface Unit is a fully integrat-

ed transceiver for T1 long haul applications. The

transmitter outputs all pulse shapes for T1 applica-

tions.

2.1

Interface Modes

The CS61310 can be operated as a stand-alone

device with its interface in hardware mode (MODE

pin is low), or it can be operated by a microcontrol-

ler over a serial interface in host mode (MODE pin

is high). Host mode enables the use of additional

functionality, as described in the Serial Interface

section.

2.2

Master Clocks

The CS61310 requires a reference clock for the re-

ceiver and the jitter attenuator. A 1.544 MHz exter-

nal clock can be input to MCLK, or a 4x crystal can

be connected to the on-chip oscillator. This fre-

quency reference should be within +32 ppm of the

nominal operating frequency. Jitter and wander on

the reference clock will degrade jitter attenuation

and receiver jitter tolerance. If MCLK is provided,

the crystal oscillator is ignored.

2.3

Transmitter

The transmitter accepts digital T1 input data and

drives appropriately shaped AMI (Alternate Mark

Inversion) pulses onto a transmission line through

a transformer. The transmit data (TPOS & TNEG

or TDATA) is sampled on the falling edge of the in-

put clock, TCLK.

The pulse shapes comply with FCC Part 68 Option

A (0 dB), Option B (-7.5 dB), Option C (-15 dB) or

(-22.5 dB) (see Table 1). Pulse shaping and signal

level are controlled by LBO1 and LBO2 pins in

hardware mode, or the LBO1 and LBO2 bits

(CR1.3 and CR1.4) in host mode.

Custom transmit pulse shapes may be implement-

ed by writing pulse shape coefficients to the regis-

ters. Custom pulses may be used to correct for

pulse shape degradation or distortion caused by

improper termination, suboptimal interconnect wir-

ing, or loading from external components such as

high voltage protection devices.

For DS-1 applications, the arrangement in Table 1

meets ANSI T1.102 pulse shape requirements. A

typical output pulse is shown in Figure 6. These

pulse settings can also be used to meet ITU-T

pulse shape requirements for 1.544 MHz opera-

tion.

Setting TNEG high for more than 16 TCLK cycles

enables the coder mode, changing TPOS to TDA-

TA, RPOS to RDATA, and RNEG to BPV. When

configured for coder mode, the MODE pin can be

tied to RCLK enabling the B8ZS encoders and de-

coders.

The CS61310 will detect the absence of TCLK,

and will force TTIP and TRING to high impedance

LBO2

LBO1

Output Pulse

0 dB

-7.5 dB

-15 dB

-22.5 dB

Table 1. Pulse Shape Selection and Transformer

Requirements

Figure 6. Typical Pulse Shape for DS-1

500

1.0

0.5

-0 .5

250

750

1 000

T IM E (nanoseconds)

OU T P U T

PU L S E S H A P E

NO RM A L IZE D

AM P L IT U D E

AN SI T I.1 0 2

SPEC IFIC AT IO N

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