CS61310 datasheet(12/30 Pages) CIRRUS

12 / 30 page

CS61310

DS440F1 FEB ‘03

2.8

Local Loopback

In hardware mode, local loopback is selected by

setting the LLOOP pin high (CR1.6 = 1 in host

mode). Selecting local loopback causes clock and

data presented on TCLK, TPOS/TNEG (TDATA) to

be output at RCLK, RPOS/RNEG (RDATA). Local

loopback disconnects the RTIP/RRING inputs

from the line. Inputs to the transmitter are still

transmitted on TTIP and TRING, unless TAOS has

been selected in which case, AMI-encoded contin-

uous ones are transmitted at the TCLK frequency.

The receiver RTIP and RRING inputs are ignored

when local loopback is in effect.

2.9

Remote Loopback

Remote loopback is selected by setting the

RLOOP pin high in hardware mode (CR1.5 = 1 in

host mode). In remote loopback, the recovered

clock and data input on RTIP and RRING are sent

back out on the line via TTIP and TRING. Selecting

remote loopback overrides a TAOS request. The

recovered clock is also sent to RCLK, and the re-

covereddatais alsosent toRPOSand RNEGinbi-

polar

mode,

RDATA

unipolar

mode.

Simultaneous selection of local and remote loop-

back modes will cause a device reset to occur (see

Reset).

2.10

Network Loopback

Network Loopback (automatic remote loopback)

can be commanded from the network when the

Network Loopback detect function is enabled. In

Host Mode, Network Loopback (NLOOP) detection

is enabled by writing ones to TAOS, LLOOP, and

RLOOP, then clearing these three bits on a suc-

cessive write cycle. In hardware mode, Network

Loopback can be enabled by tying RLOOP to

RCLK or by setting TAOS, LLOOP, and RLOOP

high for at least 200 ns, and then low. Once en-

abled Network Loopback functionality will remain

in effect until RLOOP is activated or the device is

reset.

When NLOOP detection is enabled, the receiver

monitors the input data stream for the NLOOP data

patterns (00001 = enable, 001 = disable). When an

NLOOP enable data pattern is repeated for a min-

imum of five seconds (with less than 10E-3 BER),

the device initiates a remote loopback. Once Net-

work Loopback detection is enabled and activated

by the NLOOP data pattern, the loopback is identi-

cal to Remote Loopback initiated at the device.

NLOOP is reset if the disable pattern (001) is re-

ceived for 5 seconds, or by activation of RLOOP.

NLOOP is temporarily suspended by LLOOP, but

theNLOOP stateis not reset.

2.11

Alarm Indication Signal

The receiver sets the register bit, AIS, to “1” when

less than 9 zeros are detected out of 8192 bit peri-

ods. AIS returns to “0” upon the first read after the

AIS condition is removed, determined by 9 or more

zeros out of 8192 bit periods.

2.12

Serial Interface

In the Host Mode, pins 24 through 28 serve as a

microcontroller interface. On-chip registers can be

writtentovia theSDI pinorreadfrom via theSDO

pin at the clock rate determined by SCLK. Through

these registers, a host controller can be used to

control operational characteristics and monitor de-

vice status. The serial port read/write timing is in-

dependent of the system transmit and receive

timing.

Data transfers are initiated by taking the chip select

input, CS,low (CS must initially be high). Address

and input data bits are clocked in on the rising edge

of SCLK. The clock edge on which output data is

stable and valid is determined by CLKE as shown

in Table 2. Data transfers are terminated by setting

CS high. CS may go high no sooner than 50 ns af-

ter the rising edge of the SCLK cycle correspond-

ing to the last write bit. For a serial data read, CS

may go high any time to terminate the output and

set SDO to high impedance.

Figure 10 shows the timing relationships for data

transfers when CLKE = 0. When CLKE = 1, data bit

D7 is held until the falling edge of the 16th clock cy-

cle. When CLKE = 0, data bit D7 is held valid until

the rising edge of the 17th clock cycle. SDO goes

high-impedance after CS goes high or at the end of

theholdperiodof databit D7.

SDO goes to a high impedance state when not in

use. SDO and SDI may be tied together in applica-

tions where the host processor has a bi-directional

I/O port.

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