CS61310

22

DS440F1 FEB ‘03

LBO1, LBO2 - Line Build Out 1 and 2, Pins 24 and 25 (Hardware Mode).

Transmitted line build out pulse shapes are selected by setting LBO1/2: 0/0 = 0 dB, 0/1 =

-7.5 dB, 1/0 = -15 dB, and 1/1 = -22.5 dB.

RLOOP - Remote Loopback Input, Pin 26 (Hardware Mode).

Setting RLOOP to a logic 1 causes the received signal to be passed through the jitter attenuator (if

active) and retransmitted onto the line. The internal encoders/decoders will be bypassed in Remote

Loopback. Simultaneously setting RLOOP and LLOOP high while TAOS is low resets the CS61310.

Simultaneously setting RLOOP, LLOOP and TAOS high enables Network Loopback detection.

LLOOP - Local Loopback Input, Pin 27(Hardware Mode).

Setting LLOOP to a logic 1 internally routes the transmitter input to the receiver output. If TAOS is low,

the signal being output from the transmitter will be internally routed to the receiver inputs allowing nearly

the entire chip to be tested. If TAOS and LLOOP are set high at the same time, the local loopback will

occur at the jitter attenuator (excluding the transmit and receive circuitry) and the transmitter will

transmit all ones. Simultaneously setting RLOOP and LLOOP high while TAOS is low resets the

CS61310. Simultaneously setting RLOOP, LLOOP and TAOS high enables Network Loopback detection.

TAOS - Transmit All Ones Select Input, Pin 28 (Hardware Mode).

Setting TAOS to logic 1 causes continuous ones to be transmitted at the TCLK frequency. When TAOS

is high, TPOS and TNEG (TDATA) are not output at the TTIP/TRING pins. TAOS is overridden by

Remote Loopback. Setting TAOS, LLOOP, and RLOOP high simultaneously enables Network Loopback

detection.

Status

LOS - Loss Of Signal Output, Pin 12.

LOS goes high when 175 consecutive zeros are received. LOS returns low when the ones density

reaches 12.5% (based on 175 consecutive bit periods, starting with a one and containing less than 100

consecutive zeros, as prescribed in ANSI T1.231-1993).

LATN - Line Attenuation Indication Output, Pin 18.

LATN is an encoded output that indicates the receive equalizer gain setting in relation to a five RCLK

cycle period. If LATN is high for one RCLK cycle, the equalizer is set for 7.5 dB gain, two cycles =

15 dB gain, three cycles = 22.5 dB gain, four cycles = 0 dB. LATN may be sampled on the rising edge

of RCLK.

NLOOP - Network Loopback Output, Pin 23 (Hardware Mode).

NLOOP goes high when a 00001 pattern is received for five seconds putting the CS61310 into network

(remote) loopback. Network loopback is deactivated upon receipt of a 001 pattern for five seconds, or

by the selection of RLOOP. Network loopback is temporarily suspended with LLOOP, but the state of the

NLOOP pin does not change.

Serial Control Interface

INT - Interrupt Output, Pin 23 (Host Mode).

INT pulls low to flag the host processor when NLOOP, AIS or LOS changes state. INT is an open drain

output and should be tied to the supply through a resistor.

SDI - Serial Data Input, Pin 24 (Host Mode).

Data input to the on-chip register is sampled on the rising edge of SCLK.