V62SLASH12615-01XE-R datasheet(78/98 Pages) TI1

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Pin 19 (PFBOUT)

Pin 16 (PFBIN1)

Pin 30 (PFBIN2)

10 PF

0.1 PF

DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Application and Implementation

Figure 6-4. Power Feedback Connection

6.2.1.4

Power Down and Interrupt

The power down and interrupt functions are multiplexed on pin 7 of the device. By default, this pin

functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR

(0x11h) will configure the pin as an active low interrupt output.

6.2.1.4.1 Power Down Control Mode

The PWR_DOWN/INT pin can be asserted low to put the device in a power down mode. This is equivalent

to setting bit 11 (power down) in the basic mode control register, BMCR (0x00h). An external control

signal can be used to drive the pin low, overcoming the weak internal pullup resistor. Alternatively, the

device can be configured to initialize into a power down state by use of an external pulldown resistor on

the PWR_DOWN/INT pin. Since the device will still respond to management register accesses, setting the

INT_OE bit in the MICR register will disable the PWR_DOWN/INT input, allowing the device to exit the

power down state.

6.2.1.4.2 Interrupt Mechanisms

The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting

bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output, dependent on the interrupt mask set in

the lower byte of the MISR (0x12h). The PWR_DOWN/INT pin is asynchronously asserted low when an

interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the

MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the

MISR clears ALL pending interrupts.

Example: To generate an interrupt on a change of link status or on a change of energy detect power state,

the steps would be:

•

Write 0003h to MICR to set INTEN and INT_OE

•

Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN

•

Monitor PWR_DOWN/INT pin

When PWR_DOWN/INT pin asserts low, user would read the MISR register to see if the ED_INT or

LINK_INT bits are set, i.e. which source caused the interrupt. After reading the MISR, the interrupt bits

should clear and the PWR_DOWN/INT pin will deassert.

6.2.1.5

Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed

below, others may be compatible following the requirements listed in Table 6-4. It is recommended that

the magnetics include both an isolation transformer and an integrated common mode choke to reduce

EMI. When doing the layout, do not run signals under the magnetics. This could cause unwanted noise

crosstalk. Likewise void the planes under discrete magnetics, this will help prevent common mode noise

coupling. To save board space and reduce component count, an RJ-45 with integrated magnetics may be

used.

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