V62SLASH12615-01XE-R datasheet(74/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

Table 5-29. Energy Detect Control (EDCR), Address 0x1D (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

ED_BURST_DIS

0, RW

Energy Detect Bust Disable:

Disable bursting of energy detect data pulses. By default, Energy

Detect (ED) transmits a burst of 4 ED data pulses each time the CD is

powered up. When bursting is disabled, only a single ED data pulse

will be send each time the CD is powered up.

ED_PWR_STATE

0, RO

Energy Detect Power State:

Indicates current Energy Detect Power state. When set, Energy

Detect is in the powered up state. When cleared, Energy Detect is in

the powered down state. This bit is invalid when Energy Detect is not

enabled.

ED_ERR_MET

0, RO/COR

Energy Detect Error Threshold Met:

No action is automatically taken upon receipt of error events. This bit

is informational only and would be cleared on a read.

ED_DATA_MET

0, RO/COR

Energy Detect Data Threshold Met:

The number of data events that occurred met or surpassed the

Energy Detect Data Threshold. This bit is cleared on a read.

7:4

ED_ERR_COUNT

0001, RW

Energy Detect Error Threshold:

Threshold to determine the number of energy detect error events that

should cause the device to take action. Intended to allow averaging of

noise that may be on the line. Counter will reset after approximately 2

seconds without any energy detect data events.

3:0

ED_DATA_COUNT

0001, RW

Energy Detect Data Threshold:

Threshold to determine the number of energy detect events that

should cause the device to take actions. Intended to allow averaging

of noise that may be on the line. Counter will reset after approximately

2 seconds without any energy detect data events.

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