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V62/12615-01XE-R датащи(PDF) 18 Page - Texas Instruments |
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V62/12615-01XE-R датащи(HTML) 18 Page - Texas Instruments |
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18 / 98 page ![]() TX_CLK TX_EN TXD PMD output pair (T/R) T2.7.1 IDLE DATA 18 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DP83848-EP Specifications Copyright © 2012–2019, Texas Instruments Incorporated (1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100-Mbps mode. 4.7.7 100BASE-TX Transmit Packet Deassertion Timing PARAMETER DESCRIPTION NOTES(1) MIN TYP MAX UNIT T2.7.1 TX_CLK to PMD output pair deassertion 100-Mbps Normal mode 6 bits Figure 4-8. 100BASE-TX Transmit Packet Deassertion Timing |
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