V62SLASH12615-01XE-R datasheet(40/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

Table 5-3. Supported Packet Sizes at ±50 ppm ±100 ppm for Each Clock

Start Threshold RBR[1:0]

Latency Tolerance

Recommended Packet Size

at ±50 ppm

Recommended Packet Size

at ±100 ppm

1 (4-bits)

2 bits

2,400 bytes

1,200 bytes

2 (8-bits)

6 bits

7,200 bytes

3,600 bytes

3 (12-bits)

10 bits

12,000 bytes

6,000 bytes

0 (16-bits)

14 bits

16,800 bytes

8,400 bytes

5.4.2.1

10 Mb Serial Network Interface (SNI)

The DP83848-EP incorporates a 10-Mb serial network interface (SNI) which allows a simple serial data

interface for 10-Mb only devices. This is also referred to as a 7-wire interface. While there is no defined

standard for this interface, it is based on early 10-Mb physical layer devices. Data is clocked serially at

10 MHz using separate transmit and receive paths. The following pins are used in SNI mode:

•

TX_CLK

•

TX_EN

•

TXD[0]

•

RX_CLK

•

RXD[0]

•

CRS

•

COL

5.4.3

802.3u MII Serial Management Interface

5.4.3.1

Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that

are accessible through the management interface pins MDC and MDIO. The DP83848-EP implements all

the required MII registers as well as several optional registers. These registers are fully described in

Section 5.6.

5.4.3.2

Serial Management Access Protocol

The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data

Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is

bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 5-

Table 5-4. Typical MDIO Frame Format

MII Management Serial Protocol

Read Operation

Write Operation

The MDIO pin requires a pullup resistor (1.5 k

Ω) which, during IDLE and turnaround, will pull MDIO high.

In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous

logic ones on MDIO to provide the DP83848-EP with a sequence that can be used to establish

synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pullup resistor to pull the MDIO pin high during which time 32

MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if

an invalid start, opcode, or turnaround bit is detected.

The DP83848-EP waits until it has received this preamble sequence before responding to any other

transaction. Once the DP83848-EP serial management port has been initialized no further preamble

sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit

has occurred.

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