V62SLASH12615-01XE-R datasheet(65/98 Pages) TI1

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DP83848-EP

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SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

5.6.2

Extended Registers

5.6.2.1

PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed

information.

Table 5-18. PHY Status Register (PHYSTS), Address 0x10

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESERVED

0, RO

RESERVED: Write ignored, read as 0

MDI-X Mode

0, RO

MDI-X mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and

FORCE_MDIX bits in the PHYCR register. When MDIX is enabled,

but not forced, this bit will update dynamically as the Auto-MDIX

algorithm swaps between MDI and MDI-X configurations.

1 = MDI pairs swapped

(Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal

(Receive on TRD pair, Transmit on TPTD pair)

Receive Error Latch

0, RO/LH

Receive Error Latch:

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT

(address 0x15, Page 0)

0 = No receive error event has occurred

Polarity Status

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will

be cleared upon a read of the 10BTSCR register, but not upon a read

of the PHYSTS register.

1 = Inverted Polarity detected

0 = Correct Polarity detected

False Carrier Sense

Latch

0, RO/LH

False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR

(address 0x14)

0 = No False Carrier event has occurred

Signal Detect

0, RO/LL

100Base-TX unconditional Signal Detect from PMD

Descrambler Lock

0, RO/LL

100Base-TX Descrambler Lock from PMD

Page Received

0, RO

Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register, but

this bit will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on read

of the ANER (address 0x06, bit 1)

0 = Link Code Word Page has not been received

MII Interrupt

0, RO

MII Interrupt Pending:

1 = Indicates that an internal interrupt is pending. Interrupt source can

be determined by reading the MISR Register (0x12h). Reading the

MISR will clear the Interrupt.

0= No interrupt pending

Remote Fault

0, RO

Remote Fault:

1 = Remote Fault condition detected (cleared on read of BMSR

(address 01h) register or by reset). Fault criteria: notification from Link

Partner of Remote Fault via Auto-Negotiation.

0 = No remote fault condition detected

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