V62SLASH12615-01XE-R datasheet(38/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

5.3.6

Energy Detect Mode

When Energy Detect is enabled and there is no activity on the cable, the DP83848-EP will remain in a low

power mode while monitoring the transmission line. Activity on the line will cause the DP83848-EP to go

through a normal power up sequence. Regardless of cable activity, the DP83848-EP will occasionally

wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible.

Energy detect functionality is controlled via register Energy Detect Control (EDCR), address 0x1Dh.

5.4

Device Functional Modes

The DP83848-EP supports several modes of operation using the MII interface pins. The options are

defined in the following sections and include:

•

MII mode

•

RMII mode

•

10-Mb serial network interface (SNI)

The modes of operation can be selected by strap options or register control. For RMII mode, it is required

to use the strap option, since it requires a 50-MHz clock instead of the normal 25 MHz.

In each of these modes, the IEEE 802.3 serial management interface is operational for device

configuration and status. The serial management interface of the MII allows for the configuration and

control of multiple PHY devices, gathering of status, error information, and the determination of the type

and capabilities of the attached PHY(s).

5.4.1

MII Interface

The DP83848-EP incorporates the Media Independent Interface (MII) as specified in Clause 22 of the

IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100-Mbps

systems. This section describes the nibble-wide MII data interface.

The nibble-wide MII data interface consists of a receive bus and a transmit bus each with control signals

to facilitate data transfer between the PHY and the upper layer (MAC).

5.4.1.1

Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface

includes a dedicated receive bus and a dedicated transmit bus. These two data buses, along with various

control and status signals, allow for the simultaneous exchange of data between the DP83848-EP and the

upper layer agent (MAC).

The receive interface consists of a nibble-wide data bus RXD[3:0], a receive error signal RX_ER, a

receive data valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The

receive clock operates at either 2.5 MHz to support 10-Mbps operation modes or at 25 MHz to support

100-Mbps operational modes.

The transmit interface consists of a nibble-wide data bus TXD[3:0], a transmit enable control signal

TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz.

Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The

CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in

Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-

duplex operation when both a transmit and receive operation occur simultaneously.

5.4.1.2

Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit

channels are active simultaneously. Collisions are reported by the COL signal on the MII.

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