V62SLASH12615-01XE-R datasheet(42/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

5.4.4

PHY Address

The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin are shown below.

Table 5-5. PHY Address Mapping

Pin No.

PHYAD Function

RXD Function

PHYAD0

COL

PHYAD1

RXD_0

PHYAD2

RXD_1

PHYAD3

RXD_2

PHYAD4

RXD_3

The DP83848-EP can be set to respond to any of 32 possible PHY addresses via strap pins. The

information is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware

reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848-EP or port sharing

an MDIO bus in a system must have a unique physical address.

The DP83848-EP supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). Strapping

PHY Address 0 puts the part into Isolate Mode. It should also be noted that selecting PHY Address 0 via

an MDIO write to PHYCR will not put the device in Isolate Mode. See Section 5.4.4.1 for more information.

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other

hardware configuration pins, refer to the Reset summary in Section 5.4.6.

Because the PHYAD[0] pin has weak internal pullup resistor and PHYAD[4:1] pins have weak internal

pulldown resistors, the default setting for the PHY address is 00001 (0x01h).

Refer to Figure 5-4 for an example of a PHYAD connection to external components. In this example, the

PHYAD strapping results in address 000101 (0x03h).

Figure 5-4. PHYAD Strapping Example

5.4.4.1

MII Isolate Mode

The DP83848-EP can be put into MII Isolate mode by writing to bit 10 of the BMCR register or by

strapping in Physical Address 0. It should be noted that selecting Physical Address 0 via an MDIO write to

PHYCR will not put the device in the MII isolate mode.

When in the MII isolate mode, the DP83848-EP does not respond to packet data present at TXD[3:0],

TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0],

COL, and CRS outputs. When in Isolate mode, the DP83848-EP will continue to respond to all

management transactions.

While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source

100BASE-TX scrambled idles or 10BASE-T normal link pulses.

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