V62SLASH12615-01XE-R datasheet(66/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

Table 5-18. PHY Status Register (PHYSTS), Address 0x10 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

Jabber Detect

0, RO

Jabber Detect: This bit only has meaning in 10 Mbps mode

This bit is a duplicate of the Jabber Detect bit in the BMSR register,

except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected

0 = No Jabber

Auto-Neg Complete

0, RO

Auto-Negotiation Complete:

1 = Auto-Negotiation complete

0 = Auto-Negotiation not complete

Loopback Status

0, RO

Loopback:

1 = Loopback enabled

0 = Normal operation

Duplex Status

0, RO

Duplex:

This bit indicates duplex status and is determined from Auto-

Negotiation or Forced Modes.

1 = Full duplex mode

0 = Half duplex mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete

and there is a valid link or if Auto-Negotiation is disabled and there is

a valid link.

Speed Status

0, RO

Speed10:

This bit indicates the status of the speed and is determined from Auto-

Negotiation or Forced Modes.

1 = 10 Mbps mode

0 = 100 Mbps mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete

and there is a valid link or if Auto-Negotiation is disabled and there is

a valid link.

Link Status

0, RO

Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will not be cleared upon a read of the PHYSTS register.

1 = Valid link established (for either 10 or 100 Mbps operation)

0 = Link not established

5.6.2.2

MII Interrupt Control Register (MICR)

This register implements the MII interrupt PHY specific control register. Sources for interrupt generation

include: energy detect state change, link state change, speed status change, duplex status change, auto-

negotiation complete or any of the counters becoming half-full. The individual interrupt events must be

enabled by setting bits in the MII interrupt status and event control register (MISR).

Table 5-19. MII Interrupt Control Register (MICR), Address 0x11

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:3

RESERVED

0, RO

Reserved: Write ignored, Read as 0

TINT

0, RW

Test Interrupt:

Forces the PHY to generate an interrupt to facilitate interrupt testing.

Interrupts will continue to be generated as long as this bit remains set.

1 = Generate an interrupt

0 = Do not generate interrupt

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