LTC2000 datasheet(28/54 Pages) AD

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LTC2000

2000fb

For more information www.linear.com/LTC2000

OPERATION

For single port operation, set DATA_SP = 1, DA_EN = 0,

DB_EN = 1 and provide data to LVDS port B (DBP/N) only.

For dual port operation leave DATA_SP = 0, set DA_EN =

1 and DB_EN = 1, and provide interleaved data to LVDS

ports A and B (DAP/N, DBP/N). The data on port A will

precede the data on port B at the DAC output.

Table 5. LVDS Data Input SPI Registers

ADDRESS BIT

NAME

DESCRIPTION

0x04

DA_EN

DAC Data Port A LVDS Receiver Enable. DA_EN = 1 enables port A receivers. For DA_EN = 0, receivers are powered

down and port A data is 0x0000.

DB_EN

DAC Data Port B LVDS Receiver Enable. DB_EN = 1 enables port B receivers. For DB_EN = 0, receivers are powered

down and port B data is 0x0000.

DATA_SP DAC Data Single Port Mode Select. DATA_SP = 1 sets single port mode and only port B data is used to update the DAC

code. DATA_SP = 0 sets dual-port mode and data from both ports A and B are used.

DATA_EN DAC Data Enable. DATA_EN = 0 mutes the DAC output by forcing the DAC code to mid-scale. DATA_EN = 1 allows data

from data ports A and B to be used to update the DAC code.

Note: Register 0x04 resets to 0x00 (default).

Clock Synchronizer

Figure 7 shows a simplified block diagram of the internal

clock synchronizer. The synchronizer monitors the incom-

ing phase of DCKIP/N using a pair of internal phase com-

parators. The synchronizer then automatically adjusts the

50Ω

IOUTP

IOUTN

50Ω

2000 F07

÷4

DBP/N[15:0]

DAP/N[15:0]

DCKIP/N

CKP/N

SYNC_PS

LOGIC

PHASE

CMP

PHASE

CMP

16-BIT DAC

Figure 7. Simplified Block Diagram — Clock Synchronizer in Dual-Port Mode

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