LTC2000 datasheet(37/54 Pages) AD

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LTC2000

2000fb

For more information www.linear.com/LTC2000

APPLICATIONS INFORMATION

the differential clock signal need to have accurately con-

trolled impedance and accurate termination as close to

the CKP/N pins of the LTC2000 as possible.

There are several ways to generate the DAC sample clock.

For lab evaluation and testing, a high quality RF signal

generator can provide a clean high frequency sine wave

that is converted to the DAC sample clock with a 1:1 RF

transformer or balun (see Figure 12).

A more integrated clock source is one based on a low

phase noise, low jitter PLL. Figure 13 shows how the

DAC sample clock can be generated from the LTC6946,

a high performance PLL with an internal VCO that can

provide output frequencies from 0.37GHz to 5.7GHz. See

the LTC6946 data sheet for details.

Synchronizing Multiple LTC2000s in Dual-Port Mode

In some applications, it is necessary to synchronize mul-

tiple LTC2000s to each other such that related samples

arrive at all DAC outputs simultaneously. Figures 14

and 15a show a block diagram and sample waveforms

for such a system in which two DACs (X and Y) are to be

synchronized in dual-port mode.

Note that in this example a small timing skew between the

two data signals at the DCKIP/N pins of DACs X and Y has

caused the DCKIP/N rising edges to arrive on opposite

sides of a DAC sample clock (CKP/N) rising edge, and

thus within different CKP/N clock cycles. As a result the

default behavior is for the output of DAC Y to update with

sample N one cycle earlier than the output of DAC X. It

is possible to correct this misalignment and synchronize

DACs X and Y by adjusting the clock synchronizer settings

to subtract one cycle of latency from DAC X, as shown in

the adjusted waveform at the bottom of Figure 15a. See

the Clock Synchronizer section and Figure 7 for more

details on the operation of the clock synchronizer.

In order to synchronize multiple DACs as shown in

Figures 14 and 15a, distribute the DAC sample clock

carefully with matched delays so that it arrives at the

CKP/N pins of all DACs simultaneously. Any remain-

ing timing mismatch between sample clocks will

appear directly as mismatch in the DAC output tim-

ing. Ensure that the timing mismatch between LVDS

data clock signals at the DCKIP/N pins of all DACs is

less than 0.4 cycles of the DAC sample clock, minus

any timing mismatch between the DAC sample clocks.

Be sure to maintain sufficient matching between the tim-

ing of the LVDS data inputs (DAP/N, DBP/N) and DCKIP/N

for each DAC to meet the setup and hold time specifica-

tions (t11, t12) in the Timing Characteristics section.

÷N = 250

÷O = 1

N_DIV

÷R = 10

fPFD

REF±

(fREF)

fREF*

100pF

68nH

LTC6946

KPFD

fVCO

KVCO

ICP =

11.2mA

VRF

LOOP FILTER

LF(s)

2000 F13

TUNE

453Ω

50Ω

100pF

0.022µF

R_DIV

O_DIV

RF±

*CRYSTEK CVHD-950-100.000 100MHz OSCILLATOR

RF+

RF–

(fRF)

2700pF

68nH

CKP

CKN

LTC2000

Figure 13. DAC Sample Clock Generation with the LTC6946

Figure 12. DAC Sample Clock Generation with an

RF Signal Generator and a 1:1 Balun

50Ω

•

50Ω

100pF

LTC2000 F12

1nF

50Ω

LTC2000

MINI-CIRCUITS

TC1-1-13M

RF SIGNAL

GENERATOR

CKP

CKN

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