LTC2000 datasheet(36/54 Pages) AD

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LTC2000

2000fb

For more information www.linear.com/LTC2000

APPLICATIONS INFORMATION

7. Write 0x03 to address 0x04 for dual-port mode, or

write 0x06 to address 0x04 for single-port mode to

enable the DAP/N and DBP/N LVDS receivers.

8. Wait at least 1ms for the synchronizer to finish

initializing.

9. Write 0x0B to address 0x04 for dual-port mode, or

write 0x0E to address 0x04 for single-port mode to

set DATA_EN = 1.

10. Apply desired data pattern to ports A and B (DAP/N,

DBP/N) for dual-port mode, or only to port B for single-

port mode. Port A samples will precede port B sam-

ples at the DAC output when using dual-port mode.

Output Configurations

The LTC2000’s complementary current outputs (IOUTP/N)

source current into an external load referenced to GND.

Output load configuration, component selection, and lay-

out are critical to the performance of the LTC2000. For

best AC performance, the output stages should be con-

figured for differential (or balanced) operation.

A differential resistor loaded output is a very simple output

stage. Well matched resistors are connected between GND

and IOUTP/N, with the resistance values setting both the

output swing and non-zero output common-mode voltage

(Figure 9). While it is economical, this type of output stage

IOUTP

2000 F09

LTC2000

IOUTN

Figure 9. Differential Resistor Output Load

Figure 10. Transformer-Based Output Configuration

for Differential to Single-Ended Conversion

IOUTP

2000 F10

LTC2000

MINI-CIRCUITS

TC1-1-13M

MINI-CIRCUITS

JTX-2-10T

•

IOUTN

•

can drive only differential loads with impedance levels and

amplitudes appropriate for the DAC outputs.

Differential transformer-coupled output configurations

usually give the best AC performance and provide excel-

lent rejection of common mode distortion and noise over

a broad frequency range. Figure 10 shows a transformer

output configuration that uses a Mini-Circuits TC1-1-13M

and a JTX-2-10T RF transformer for differential to single-

ended conversion.

For any output configuration, any imbalances in the out-

put impedance between the IOUTP and IOUTN pins results in

asymmetrical signal swings that lead to distortion (mostly

even order). Careful consideration is needed to select the

best output configuration for a given application.

Generating the DAC Sample Clock

For best AC performance, it is important that the DAC

sample clock waveforms be clean, with low phase noise

and good jitter performance, as the phase noise and spu-

rious content of the clock source will appear directly in

the DAC output spectrum.

A differential clock should be AC coupled onto the CKP/N

pins, since the DC bias point of CKP/N is set internally to

1V through a 5kΩ impedance. Figure 11 shows the DAC

sample clock receiver input and common-mode voltage

control. While the differential input voltage range of the

clock receiver spans from ±300mV to ±1.8V, a signal

with the highest possible slew rate and amplitude and a

balanced duty cycle is recommended. Traces that carry

Figure 11. DAC Sample Clock Receiver

AVDD18

LTC2000

CKP

CKN

GND

2000 F11

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