LTC2000 datasheet(34/54 Pages) AD

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LTC2000

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SPI REGISTER SUMMARY

Table 11. SPI Register List

ADDRESS

BIT

NAME

DESCRIPTION

RESET

VALUE

R/W

0x00

[7:0]

Reserved

0x01

SW_RST

Software Reset. SW_RST = 1 resets all registers.

R/W

DAC_PD

DAC Power Down. DAC_PD = 1 to power down DAC core.

R/W

FULL_PD

Full Power Down. FULL_PD = 1 to power down LTC2000.

R/W

Reserved

[5:4]

DAC_RES

DAC Resolution Indicator. DAC_RES = 00 for LTC2000-16. DAC_RES = 01 for LTC2000-14.

DAC_RES = 11 for LTC2000-11. Note that for PD = GND or FULL_PD = 1, DAC_RES = 00.

DAC_RES is read only.

00-16b

01-14b

11-11b

[7:6]

Reserved

0x02

CK_PD

CKP/N Clock Receiver Power Down. CK_PD = 1 disables

R/W

CK_OK

CKP/N Clock Present Indicator. CK_OK = 1 clock present

[3:2]

Reserved

DCKO_DIS

DCKOP/N Output Disable. DCKO_DIS = 1 disables

R/W

DCKO_DIV

DCKOP/N Divide Select. (0 = fDAC/4, 1 = fDAC/2).

R/W

DCKO_ISEL

DCKOP/N Output Current Select. (0=3.5mA, 1 = 7mA)

R/W

DCKO_TRM

DCKOP/N Internal Termination On. DCKO_TRM = 1 enables internal 100Ω termination

R/W

0x03

DCKI_EN

DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables.

R/W

DCKI_OK

DCKIP/N Clock Present Indicator. DCKI_OK = 1 indicates clock present

DCKI_Q

DCKIP/N Quadrature Phase Select. (0 = In Phase, 1 = Quadrature)

R/W

Reserved

[6:4]

DCKI_TADJ

DCKIP/N Delay Adjust. (See Table 4)

000

R/W

Reserved

0x04

DA_EN

Port A LVDS Receiver Enable. DA_EN = 1 to enable

R/W

DB_EN

Port B LVDS Receiver Enable. DB_EN = 1 to enable

R/W

DATA_SP

Port Mode Select. (0 = Dual port, 1 = Single port)

R/W

DATA_EN

DAC Data Enable. DATA_EN = 0 forces DAC output to mid-scale.

R/W

[7:4]

Reserved

0x05

[1:0]

SYNC_PS

Clock Synchronizer Phase Select.

R/W

SYNC_MSYN Clock Synchronizer Manual Mode Select.

SYNC_MSYN = 0: SYNC_PS is set automatically.

SYNC_MSYN = 1: SYNC_PS is set by the user.

R/W

[7:3]

Reserved

0x06

[7:0]

SYNC_PH

Clock Phase Comparator Outputs. (See Table 6)

0x00

Table 10 – Pattern Generator SPI Registers

ADDRESS

BIT

NAME

DESCRIPTION

0x1E

PGEN_EN Pattern Generator Enable. Set PGEN_EN = 1 to use the internal 64 sample pattern generator to provide data to the DAC.

Set DATA_SP = 0, DCKO_DIV = 0, and DATA_EN = 1 when PGEN_EN = 1.

0x1F

[7:0]

PGEN_D

Pattern Generator Data. Write 128 bytes of data to this address to fill the pattern generator with 64 samples.

Data is written MSB first. Reading this location causes the pattern generator data to be shifted out through SDO.

Ensure PGEN_EN = 0 when reading or writing to address 0x1F. Read or write an even number of bytes to address

0x1F prior to setting PGEN_EN = 1 to avoid corrupting the data inside the pattern generator.

Note: Registers 0x1E and 0x1F reset to 0x00 (default).

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