LTC2000 datasheet(38/54 Pages) AD

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LTC2000

2000fb

For more information www.linear.com/LTC2000

APPLICATIONS INFORMATION

For example, let us consider a system using multiple

DACs at 2.5Gsps in which the sample clock is designed

to arrive at the CKP/N pins of all DACs within 30ps of

one another. The sample clock period is 400ps, so the

maximum allowable timing mismatch between the data

clock signals at the DCKIP/N pins of all DACs will be (0.4 •

400ps) – 30ps = 130ps. For a system using multiple DACs

at 1.25Gsps, the allowable mismatch between DCKIP/N

pins will be (0.4 • 800ps) – 30ps = 290ps. In both cases,

once the DACs are synchronized the mismatch in the DAC

output timing will be limited to 30ps.

Once all the DAC sample clocks and LVDS data clocks are

aligned, determine whether any DACs are being updated

one cycle late (such as DAC X in Figure 15a) by determin-

ing whether DCKIP/N is arriving at the DACs within the

same CKP/N clock cycle. To do this in dual-port mode,

first use the phase comparator outputs SYNC_PH and

Table 12 to determine the delay from the DCKIP/N rising

edge to the next CKP/N rising edge for each DAC (mea-

sured in sample clock cycles).

Recall that the DCKIP/N timing mismatch must be kept

below 0.4 cycles of the sample clock. If DCKIP/N arrives at

CKP/N

DAC X

LTC2000

DCKIP/N

LVDS DATA

LVDS CLK

MATCHED

DELAYS

MATCHED

DELAYS

DAP/N

DBP/N

CKP/N

DAC Y

LTC2000

DCKIP/N

2000 F14

LVDS DATA

LVDS CLK

DAP/N

DBP/N

CLOCK

SOURCE

FPGA

DAP/N[15:0]

N+2

N+4

N+6

N+8

N+10

DBP/N[15:0]

DAC X

DCKIP/N

DAC X

IOUTP/N

DAC X

IOUTP/N

(ADJUSTED)

DAC Y

IOUTP/N

DAC Y

DCKIP/N

CKP/N

N+1

N+3

0.9

CYCLES

0.1 CYCLES

10 CYCLES

2000 F15a

N+5

N+7

N+9

N+11

N+1

9 CYCLES

10 CYCLES

Figure 14. System with Multiple LTC2000 DACs Synchronized

Figure 15a. Sample Waveforms — Synchronizing Multiple LTC2000s in Dual Port Mode

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