LTC2000 datasheet(41/54 Pages) AD

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LTC2000

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For more information www.linear.com/LTC2000

APPLICATIONS INFORMATION

Table 13. Adjusting Latency in Single-Port Mode

PHASE COMPARATOR OUTPUTS

SYNC_PH (REG 0x06)

DELAY FROM DCKIP/N RISING

EDGE TO NEXT CKP/N FALLING

EDGE (CKP/N CYCLES)

SYNC_PS SETTING

(DEFAULT)

(ADJUSTED TO REDUCE LATENCY

BY 1 CYCLE)*

0x03

0.5 to 0.6

N/A

0x04

0.6 to 0.7

0x05

0.7 to 0.8

0x15

0.8 to 0.9

0x25

0.9 to 1.0

0x35

0 to 0.1

N/A

0x45

0.1 to 0.2

N/A

0x55

0.2 to 0.3

N/A

0x54

0.3 to 0.4

N/A

0x53

0.4 to 0.5

N/A

0x52

0.5 to 0.6

N/A

0x51

0.6 to 0.7

0x50

0.7 to 0.8

0x40

0.8 to 0.9

0x30

0.9 to 1.0

0x20

0 to 0.1

N/A

0x10

0.1 to 0.2

N/A

0x00

0.2 to 0.3

N/A

0x01

0.3 to 0.4

N/A

0x02

0.4 to 0.5

N/A

*N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs,

keep SYNC_PS as the default value.

PCB Layout Considerations

The close proximity of high frequency digital data lines

and high dynamic range, wideband analog signals make

clean printed circuit board design and layout an absolute

necessity. Figures 16 and 17 show a schematic and PCB

layers for an evaluation circuit for the LTC2000. A single,

solid ground plane should be used, while separate supply

planes for AVDD18, DVDD18, AVDD33, and DVDD33 should

be kept all the way to the individual supply or LDO. All

LVDS input (DCKIP/N, DAP/N, DBP/N) board traces must

be carefully matched to ensure proper phase alignment.

These LVDS inputs should be kept far away from both the

IOUTP/N and CKP/N traces to avoid any data dependent

coupling into the analog output and DAC sample clock.

The CKP/N traces should be routed either over the analog

ground plane or over their own section on the ground

plane. These traces also need to have accurately con-

trolled impedance and should be well terminated near

the LTC2000. The IOUTP/N traces should also be carefully

matched to each other, routed over the ground plane,

away from the LVDS inputs and CKP/N signals.

Bypass capacitors are required on AVDD18, DVDD18,

AVDD33, and DVDD33, and should all be connected to the

analog ground plane. 2.2µF ceramic capacitors with low

ESR are recommended to be placed close to the LTC2000

with minimum trace lengths. A sample PCB layout and

schematic can be found below.

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