LTC2000 datasheet(35/54 Pages) AD

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LTC2000

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SPI REGISTER SUMMARY

Table 11. SPI Register List

ADDRESS

BIT

NAME

DESCRIPTION

RESET

VALUE

R/W

0x07

LIN_DIS

Dynamic Linearization Disable. LIN_DIS = 1 disables.

R/W

[3:1]

LIN_GN

Dynamic Linearization Gain Select. (See Table 7)

000

R/W

[7:4]

Reserved

0x08

[3:0]

LIN_VMX

Dynamic Linearization Max IOUTP/N Voltage Select. (See Table 7)

1000

R/W

[7:4]

LIN_VMN

Dynamic Linearization Min IOUTP/N Voltage Select. (See Table 7)

0000

R/W

0x09

[5:0]

GAIN_ADJ

DAC Gain Adjustment. (See Table 2)

0x00

R/W

[7:6]

Reserved

0x0A Thru

0x17

[7:0]

Reserved

0x18

LMX_MSEL

LVDS Test MUX Select. (See Table 8)

R/W

[5:1]

LMX_ADR

LVDS Test MUX Address Select. (See Table 8)

0x00

R/W

LMX_EN

LVDS Test MUX Enable. LMX_EN = 1 enables LVDS text MUX. Ensure TDIO_EN = 0 when

LMX_EN = 1.

Reserved

0x19

TDIO_EN

TSTP/N Junction Temperature Diode Enable.

TDIO_EN = 1 enables temperature (TJ) measurement.

Ensure LMX_EN = 0 when TDIO_EN = 1.

R/W

TDIO_SEL

Junction Temperature Select. TDIO_SEL = 0 uses a diode-connected unbiased NPN transistor.

TDIO_SEL = 1 outputs a voltage to calculate internal die temperature using:

TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). (See Table 9)

R/W

[7:2]

Reserved

0x1A Thru

0x1D

[7:0]

Reserved

0x1E

PGEN_EN

Pattern Generator Enable. PGEN_EN = 1 enables.

R/W

[7:1]

Reserved

0x1F

[7:0]

PGEN_D

Pattern Generator Data.

0x00

R/W

0x20 Thru

0x7F

[7:0]

Reserved

APPLICATIONS INFORMATION

Sample Start-Up Sequence

The following is an example of a common start-up

sequence.

1. Apply valid supply voltages to AVDD33, DVDD33,

AVDD18, DVDD18 and SVDD.

2. Write 0x01 to address 0x01 to perform a software reset.

3. Apply a clock to CKP/N at the desired fDAC frequency.

The LTC2000 will generate a clock at DCKOP/N

at fDAC/4.

4. Apply a clock to DCKIP/N at fDAC/4 for dual-port mode

or fDAC/2 for single-port mode.

5. Apply zeroes to ports A and B (DAP/N, DBP/N) for

dual-port mode, or only to port B for single-port mode.

6. Write to address 0x03 to enable the DCKIP/N LVDS

receiver. Set address 0x03 to 0x01 if the LVDS clock

(DCKI) and data (DA, DB) are in phase with each other.

Set address 0x03 to 0x05 if they are in quadrature.

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