LTC2000 datasheet(23/54 Pages) AD

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LTC2000

2000fb

For more information www.linear.com/LTC2000

OPERATION

R/W

READ/WRITE

COMMAND BYTE

DATA BYTE

2000 F05

Figure 5. SPI Command and Data Input

Serial Peripheral Interface (SPI)

The LTC2000 uses an SPI/MICROWIRE-compatible

3-wire serial interface to configure and read back inter-

nal registers. The SVDD pin is the power supply for the

SPI interface (nominally 1.8V or 3.3V). The CS input is

level triggered. When this input is taken low, it acts as a

chip-select signal, enabling the SDI and SCK buffers and

the SPI input register. After the falling edge of CS, the first

data byte clocked into SDI by the rising edges of SCK is

the command byte. The first bit of the command byte

signifies a read (R/W = 1) or write (R/W = 0) operation.

The next seven bits contain the register address, which

completes the command byte.

The next byte transferred after the command byte is the

data byte. For write operations, the data byte is written to

the SPI register specified by the register address set in

the command byte. During read operations, the data byte

is ignored, and the contents of the selected SPI register

are clocked out onto the SDO pin by the falling edges of

SCK. During write operations, SDO will be low. When CS

goes high, SDO is high impedance. Figure 5 shows the

SPI command and data input.

Users wishing to transfer multiple bytes of data at once

may do so, with the address for each subsequent byte

automatically incremented internally. The address will

continue to increment until CS goes high or until address

bits A[4:0] reach 0x1F, after which subsequent bytes will

continue to be written to the same address.

Reserved address and bit locations should not be written

with any value other than zero. Table 11 contains a full

description of all internal SPI registers and can be found

in the SPI Register Summary section.

Power-On Reset

The internal power-on reset circuit will reset the LTC2000

upon power up and clear the output to mid-scale when

power is first applied, making system initialization con-

sistent and repeatable. All internal registers are reset to

0x00, with the exception of register address 0x08, which

resets to 0x08. A software reset can also be applied by

using the SPI interface to load 0x01 into register address

0x01, setting SW_RST to 1 (see Table 1). Note that the

SW_RST bit is automatically cleared when CS returns

high. It is recommended that users perform a software

reset once all power supplies are stable.

Power Down

Users wishing to save power when the DAC is not being

used may reduce the supply current to less than 440µA by

pulling the PD pin to GND or by writing to register 0x01

to set FULL_PD = 1. Alternatively, users may power down

unused portions of the chip individually using DAC_PD,

CK_PD, DCKO_DIS, DCKI_EN, DA_EN, and DB_EN in reg-

isters 0x01, 0x02, 0x03, and 0x04 (see Table 1).

Reference Operation

The LTC2000 has a 1.25V internal bandgap voltage ref-

erence that drives the REFIO pin through a 10k internal

resistor, and should be buffered if driving any additional

external load. For noise performance, a 0.1µF capacitor

to GND is recommended on the REFIO pin, but is not

required for stability.

In the case where an external reference would be pre-

ferred, the external reference is simply applied to the

REFIO pin and overdrives the internal reference. The

acceptable external reference range is 1.1V to 1.4V.

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