MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

22

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC755.

Figure 11. AC Test Load for the JTAG Interface

Figure 12 provides the JTAG clock input timing diagram.

Figure 12. JTAG Clock Input Timing Diagram

TRST assert time

25

—

ns

2

Input setup times:Boundary-scan data

TMS, TDI

4

0

—

—

ns

3

Input hold times:Boundary-scan data

TMS, TDI

15

12

—

—

ns

3

Valid times:Boundary-scan data

TDO

—

—

4

4

ns

4

Output hold times:Boundary-scan data

TDO

25

12

—

—

ns

4

TCK to output high impedance:Boundary-scan data

TDO

3

3

19

9

ns

4, 5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output

timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 11). Time-of-flight delays must be added

for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Parameter

Symbol

Min

Max

Unit

Notes

Output

TCLK

VM

VM

VM