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MPC755 датащи(PDF) 15 Page - Motorola, Inc |
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MPC755 датащи(HTML) 15 Page - Motorola, Inc |
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15 / 56 page ![]() MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 15 Electrical and Thermal Characteristics Figure 4 provides the mode select input timing diagram for the MPC755. Figure 4. Mode Input Timing Diagram Figure 5 provides the AC test load for the MPC755. Figure 5. AC Test Load Table 10. Processor Bus AC Timing Specifications 1 At recommended operating conditions (see Table 3) Parameter Symbol All Speed Grades Unit Notes Min Max Setup times: All inputs tIVKH 2.5 — ns Input hold times: TLBISYNC, MCP, SMI tIXKH 0.6 — ns 6 Input hold times: All inputs, except TLBISYNC, MCP, SMI tIXKH 0.2 — ns 6 Valid times: All outputs tKHOV —4.1 ns Output hold times: All outputs tKHOX 1.0 — ns SYSCLK to output enable tKHOE 0.5 — ns 2 SYSCLK to output high impedance (all except ABB, ARTRY, DBB)tKHOZ —6.0 ns 2 SYSCLK to ABB, DBB high impedance after precharge tKHABPZ —1.0 tsysclk 2, 3, 4 Maximum delay to ARTRY precharge tKHARP —1 tsysclk 2, 3, 5 HRESET Mode Signals tMVRH tMXRH VM = Midpoint Voltage (OVDD/2) VM Output Z0 = 50 Ω OVDD/2 RL = 50 Ω |
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