MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

14

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 3 provides the SYSCLK input timing diagram.

Figure 3. SYSCLK Input Timing Diagram

4.2.2 Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC755 as defined in Figure 4 and Figure 6.

Timing specifications for the L2 bus are provided in Section 4.2.3, “L2 Clock AC Specifications.”

At recommended operating conditions (see Table 3)

Parameter

All Speed Grades

Unit

Notes

Min

Max

Mode select input setup to HRESET

8—

t

sysclk

3, 4, 5,

6, 7

HRESET to mode select input hold

0

—

ns

3, 4, 6,

7, 8

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All

output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings

assume a purely resistive 50-Ω load (see Figure 5). Input and output timings are measured at the pin; time-of-flight delays must be added

for trace lengths, vias, and connectors in the system.

valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)—note

the position of the reference and its state for inputs—and output hold time can be read as the time from the rising edge (KH) until the output

went invalid (OX).

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4).

4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks

after the PLL-relock time during the power-on reset sequence.

compute the actual time duration (in ns) of the parameter in question.

6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0:3], and TLBISYNC.

7. Guaranteed by design and characterization.

8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation will cause the

bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during operation will cause the PLL division ratio

selection to change. Both of these conditions are considered outside the specification and are not supported. Once HRESET is negated the

states of the bus mode selection pins must remain stable.

SYSCLK

VM

VM

VM