MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

37

System Design Information

shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do

not comply with the 400-MHz column in Table 8.

Table 16. MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts

PLL_CFG

[0:3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Bus

33 MHz

Bus

50 MHz

Bus

66 MHz

Bus

75 MHz

Bus

80 MHz

Bus

100 MHz

0100

2x

2x

—

—

—

—

—200

(400)

1000

3x

2x

—

—

200

(400)

225

(450)

240

(480)

300

(600)

1110

3.5x

2x

—

—

233

(466)

263

(525)

280

(560)

350

(700)

1010

4x

2x

—

200

(400)

266

(533)

300

(600)

320

(640)

400

(800)

0111

4.5x

2x

—

225

(450)

300

(600)

338

(675)

360

(720)

—

1011

5x

2x

—

250

(500)

333

(666)

375

(750)

400

(800)

—

1001

5.5x

2x

—

275

(550)

366

(733)

—

—

—

1101

6x

2x

200

(400)

300

(600)

400

(800)

—

—

—

0101

6.5x

2x

216

(433)

325

(650)

—

—

—

—

0010

7x

2x

233

(466)

350

(700)

—

—

—

—

0001

7.5x

2x

250

(500)

375

(750)

—

—

—

—

1100

8x

2x

266

(533)

400

(800)

—

—

—

—

0110

10x

2x

333

(666)

—

—

—

—

—

0011

PLL off/bypass

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111

PLL off

PLL off, no core clocking occurs

Notes:

1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which

are not useful, not supported, or not tested for by the MPC755; see Section 4.2.1, “Clock AC Specifications,” for valid SYSCLK, core, and

VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1

mode operation. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL off mode, no clocking occurs inside the MPC755 regardless of the SYSCLK input.