MPC755 datasheet(42/56 Pages) MOTOROLA

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

System Design Information

additional power draw, but address bus pull-up resistors are not neccessary for proper device operation. The snooped

address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], TBST, and GBL.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not

require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that

those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are:

DH[0:31], DL[0:31], and DP[0:7].

If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their

outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not

require pull-up resistors, and should be left unconnected by the system to minimize possible output switching.

If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the

input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left

unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also

be disabled through HID0, and all parity pins may be left unconnected by the system.

The L2 interface does not require pull-up resistors.

8.7 JTAG Configuration Signals

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE

1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible

to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset

performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is

also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not

practical.

The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware

and debugging software) to access and control the internal operations of the processor. The COP interface connects

primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target

system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or

push-button switches, then the COP reset signals must be merged into these signals with logic.

The arrangement shown in Figure 24 allows the COP port to independently assert HRESET or TRST, while ensuring

that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be

tied to HRESET through a 0-

Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is

asserted ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the

COP header be designed into the system as shown in Figure 24, if this is not possible, the isolation resistor will allow

future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.

The COP header shown in Figure 24 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and can be as

inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100"

centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector

key.

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