| поискавой системы для электроныых деталей |
|
MPC755 датащи(PDF) 28 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
MPC755 датащи(HTML) 28 Page - Motorola, Inc |
|
28 / 56 page ![]() MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 28 Freescale Semiconductor Pinout Listings Table 15 provides the pinout listing for the MPC755, 360 PBGA and CBGA packages. VOLTDET F3 High Output — 6 Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and the PLL (after filtering to become AVDD). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL pin configuration of Table 2 and the voltage supplied. For actual recommended value of Vin or supply voltages, see Table 3. 2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 3. This pin must be pulled up to OVDD for proper operation of the processor interface. To allow for future I/O voltage changes, provide the option to connect BVSEL independently to either OVDD or GND. 4. Uses 1 of 15 existing no connects in the MPC740, 255 BGA package. 5. Internal pull-up on die. 6. Internally tied to GND in the MPC745, 255 BGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply input. Caution: This differs from the MPC755, 360 BGA package. Table 15. Pinout Listing for the MPC755, 360 BGA Package Signal Name Pin Number Active I/O I/F Voltage 1 Notes A[0:31] A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 High I/O OVDD AACK N3 Low Input OVDD ABB L7 Low I/O OVDD AP[0:3] C4, C5, C6, C7 High I/O OVDD ARTRY L6 Low I/O OVDD AVDD A8 — — 2.0 V BG H1 Low Input OVDD BR E7 Low Output OVDD BVSEL W1 High Input OVDD 3, 5, 6 CI C2 Low Output OVDD CKSTP_IN B8 Low Input OVDD CKSTP_OUT D7 Low Output OVDD CLK_OUT E3 — Output OVDD DBB K5 Low I/O OVDD DBDIS G1 Low Input OVDD DBG K1 Low Input OVDD DBWO D1 Low Input OVDD Table 14. Pinout Listing for the MPC745, 255 PBGA Package (continued) Signal Name Pin Number Active I/O I/F Voltage 1 Notes |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |