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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSOC4100S датащи(PDF) 25 Page - Cypress Semiconductor |
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PSOC4100S датащи(HTML) 25 Page - Cypress Semiconductor |
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25 / 42 page  PSoC® 4: PSoC 4100S Plus Datasheet Document Number: 002-19966 Rev. *F Page 25 of 42 10-bit CapSense ADC SID315G IDAC3CRT23 Output current of IDAC in 8-bit mode in medium range 69 – 82 µA LSB = 300-nA typ SID315H IDAC3CRT33 Output current of IDAC in 8-bit mode in high range 540 – 660 µA LSB = 2.4-µA typ SID320 IDACOFFSET All zeroes input – – 1 LSB Polarity set by Source or Sink. Offset is 2 LSBs for 37.5 nA/LSB mode SID321 IDACGAIN Full-scale error less offset – – ±10 % SID322 IDACMISMATCH1 Mismatch between IDAC1 and IDAC2 in Low mode –– 9.2 LSB LSB = 37.5-nA typ SID322A IDACMISMATCH2 Mismatch between IDAC1 and IDAC2 in Medium mode –– 5.6 LSB LSB = 300-nA typ SID322B IDACMISMATCH3 Mismatch between IDAC1 and IDAC2 in High mode –– 6.8 LSB LSB = 2.4-µA typ SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC – – 5 µs Full-scale transition. No external load SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC – – 5 µs Full-scale transition. No external load SID325 CMOD External modulator capacitor. – 2.2 – nF 5-V rating, X7R or NP0 cap Table 13. CSD and IDAC Specifications (continued) SPEC ID# Parameter Description Min Typ Max Units Details / Conditions Table 14. 10-bit CapSense ADC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SIDA94 A_RES Resolution – – 10 bits Auto-zeroing is required every millisecond SIDA95 A_CHNLS_S Number of channels - single ended – – 16 Defined by AMUX Bus SIDA97 A-MONO Monotonicity – – – Yes SIDA98 A_GAINERR Gain error – – ±3 % In VREF (2.4 V) mode with VDDA bypass capacitance of 10 µF SIDA99 A_OFFSET Input offset voltage – – ±18 mV In VREF (2.4 V) mode with VDDA bypass capacitance of 10 µF SIDA100 A_ISAR Current consumption – – 0.25 mA SIDA101 A_VINS Input voltage range - single ended VSSA –VDDA V SIDA103 A_INRES Input resistance – 2.2 – KΩ SIDA104 A_INCAP Input capacitance – 20 – pF SIDA106 A_PSRR Power supply rejection ratio – 60 – dB In VREF (2.4 V) mode with VDDA bypass capacitance of 10 µF SIDA107 A_TACQ Sample acquisition time – 1 – µs SIDA108 A_CONV8 Conversion time for 8-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz. – – 21.3 µs Does not include acqui- sition time. Equivalent to 44.8 ksps including acquisition time. SIDA108A A_CONV10 Conversion time for 10-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz. – – 85.3 µs Does not include acqui- sition time. Equivalent to 11.6 ksps including acquisition time. |
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