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PSoC® 4: PSoC 4100S Plus

Datasheet

Document Number: 002-19966 Rev. *F

Page 7 of 42

Watch Crystal Oscillator (WCO)

The PSoC 4100S Plus clock subsystem also implements a

low-frequency (32-kHz watch crystal) oscillator that can be used

for precision timing applications.

External Crystal Oscillators (ECO)

The PSoC 4100S Plus also implements a 4 to 33 MHz crystal

oscillator.

Watchdog Timer

A watchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the set timeout

occurs. The watchdog reset is recorded in a Reset Cause

Reset

PSoC 4100S Plus can be reset from a variety of sources

including a software reset. Reset events are asynchronous and

guarantee reversion to a known state. The reset cause is

recorded in a register, which is sticky through reset and allows

software to determine the cause of the reset. An XRES pin is

reserved for external reset by asserting it active low. The XRES

pin has an internal pull-up resistor that is always enabled.

Analog Blocks

12-bit SAR ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock

rate of 18 MHz and requires a minimum of 18 clocks at that

frequency to do a 12-bit conversion.

The Sample-and-Hold (S/H) aperture is programmable allowing

the gain bandwidth requirements of the amplifier driving the SAR

inputs, which determine its settling time, to be relaxed if required.

It is possible to provide an external bypass (through a fixed pin

location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input

sequencer. The sequencer cycles through selected channels

autonomously (sequencer scan) with zero switching overhead

(that is, aggregate sampling bandwidth is equal to 1 Msps

whether it is for a single channel or distributed over several

channels). The sequencer switching is effected through a state

machine or through firmware driven switching. A feature

provided by the sequencer is buffering of each channel to reduce

CPU interrupt service requirements. To accommodate signals

with varying source impedance and frequency, it is possible to

have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers

(low and high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

The SAR is not available in Deep Sleep mode as it requires a

high-speed clock (up to 18 MHz). The SAR operating range is

1.71 V to 5.5 V.

Figure 4. SAR ADC

Two Opamps (Continuous-Time Block; CTB)

PSoC 4100S Plus has two opamps with Comparator modes

which allow most common analog functions to be performed

on-chip eliminating external components; PGAs, Voltage

Buffers, Filters, Trans-Impedance Amplifiers, and other functions

can be realized, in some cases with external passives. saving

power, cost, and space. The on-chip opamps are designed with

enough bandwidth to drive the Sample-and-Hold circuit of the

ADC without requiring external buffering.

Low-power Comparators (LPC)

PSoC 4100S Plus has a pair of low-power comparators, which

can also operate in Deep Sleep modes. This allows the analog

system blocks to be disabled while retaining the ability to monitor

external voltage levels during low-power modes. The

comparator outputs are normally synchronized to avoid

metastability unless operating in an asynchronous power mode

where the system wake-up circuit is activated by a comparator

switch event. The LPC outputs can be routed to pins.

Current DACs

PSoC 4100S Plus has two IDACs, which can drive any of the

pins on the chip. These IDACs have programmable current

ranges.

Analog Multiplexed Buses

PSoC 4100S Plus has two concentric independent buses that go

around the periphery of the chip. These buses (called amux

buses) are connected to firmware-programmable analog

switches that allow the chip's internal resources (IDACs,

comparator) to connect to any pin on the I/O Ports.

Data and

Status Flags

Reference

Selection

External

Reference and

Bypass

(optional)

POS

NEG

SAR Sequencer

SARADC

Inputs from other Ports

VDDA /2

VDDA

VREF

AHB System Bus and Programmable Logic

Interconnect

Sequencing

and Control

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