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PSoC® 4: PSoC 4100S Plus

Datasheet

Document Number: 002-19966 Rev. *F

Page 8 of 42

Programmable Digital Blocks

Smart I/O Block

The Smart I/O block is a fabric of switches and LUTs that allows

Boolean functions to be performed in signals being routed to the

pins of a GPIO port. The Smart I/O can perform logical opera-

tions on input pins to the chip and on signals going out as

outputs.

Fixed Function Digital Blocks

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of a 16-bit counter with

user-programmable period length. There is a capture register to

record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or

auto-reload the counter when its count is equal to the period

signals that are used as PWM duty cycle outputs. The block also

provides true and complementary outputs with programmable

offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force

outputs to a predetermined state; for example, this is used in

motor drive systems when an over-current state is indicated and

the PWM driving the FETs needs to be shut off immediately with

no time for software intervention. Each block also incorporates a

Quadrature decoder. There are eight TCPWM blocks in

PSoC 4100S Plus.

Serial Communication Block (SCB)

PSoC 4100S Plus has five serial communication blocks, which

can be programmed to have SPI, I2C, or UART functionality.

I2C Mode

: The hardware I2C block implements a full

multi-master and slave interface (it is capable of multi-master

arbitration). This block is capable of operating at speeds of up to

400 kbps (Fast Mode) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

supports EZI2C that creates a mailbox address range in the

memory of PSoC 4100S Plus and effectively reduces I2C

communication to reading from and writing to an array in

memory. In addition, the block supports an 8-deep FIFO for

receive and transmit which, by increasing the time given for the

CPU to read data, greatly reduces the need for clock stretching

caused by the CPU not having read data on time.

The I2C peripheral is compatible with the I2C Standard-mode and

Fast-mode devices as defined in the NXP I2C-bus specification

and user manual (UM10204). The I2C bus I/O is implemented

with GPIO in open-drain modes.

PSoC 4100S Plus is not completely compliant with the I2C spec

in the following respect:

■ GPIO cells are not overvoltage tolerant and, therefore, cannot

be hot-swapped or powered up independently of the rest of the

I2C system.

UART Mode

: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

SPI Mode

: The SPI mode supports full Motorola SPI, TI SSP

(adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half-duplex form of SPI). The SPI block can

use the FIFO.

CAN

There is a CAN 2.0B block with support for TT-CAN.

GPIO

PSoC 4100S Plus has up to 54 GPIOs. The GPIO block imple-

ments the following:

■ Eight drive modes:

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL).

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Selectable slew rates for dV/dt related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 5 and 6). During power-on and reset,

the blocks are forced to the disable state so as not to crowbar

any inputs and/or cause excess turn-on current. A multiplexing

network known as a high-speed I/O matrix is used to multiplex

between various signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it.

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