PSOC4100S datasheet(5/42 Pages) CYPRESS

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PSoC® 4: PSoC 4100S Plus

Datasheet

Document Number: 002-19966 Rev. *F

Page 5 of 42

Figure 2. Block Diagram

PSoC 4100S Plus devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The ARM Serial-Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE provides fully integrated programming

and debug support for the PSoC 4100S Plus devices. The SWD

interface is fully compatible with industry-standard third-party

tools. PSoC 4100S Plus provides a level of security not possible

with multi-chip application solutions or with microcontrollers. It

has the following advantages:

■ Allows disabling of debug features

■ Robust flash protection

■ Allows customer-proprietary functionality to be implemented in

on-chip programmable blocks

The debug circuits are enabled by default and can be disabled

in firmware. If they are not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden

without erasing the firmware thus providing security.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. All programming, debug, and test interfaces are

disabled when maximum device security is enabled. Therefore,

PSoC 4100S Plus, with device security enabled, may not be

returned for failure analysis. This is a trade-off the PSoC 4100S

Plus allows the customer to make.

Peripherals

CPU Subsystem

System Interconnect (Single Layer AHB)

PSoC 4100S

Plus

I/ O Subsystem

Peripheral Interconnect ( MMIO)

PCLK

FLASH

128KB

Read Accelerator

SPCIF

SRAM Controller

ROM

8 KB

ROM Controller

32-bit

AHB- Lite

Up to 54 x GPIOs

DeepSleep

Active / Sleep

Power Modes

Digital DFT

Test

Analog DFT

System Resources

Lite

Power

Clock

Reset

Clock Control

IMO

Sleep Control

REF

POR

Reset Control

TestMode Entry

WIC

XRES

WDT

ILO

PWRSYS

SAR ADC

(12-bit)

CTBm

2 x Opamp

Programmable

Analog

SARMUX

High Speed I/O Matrix & Smart I/O

SWD/TC, MTB

NVIC, IRQMUX, MPU

Cortex

M0+

48 MHz

FAST MUL

SRAM

16 KB

DataWire/

DMA

Initiator / MMIO

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