PSOC4100S datasheet(6/42 Pages) CYPRESS

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PSoC® 4: PSoC 4100S Plus

Datasheet

Document Number: 002-19966 Rev. *F

Page 6 of 42

Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0+ CPU in the PSoC 4100S Plus is part of the

32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16

bits in length and the CPU executes a subset of the Thumb-2

instruction set. It includes a nested vectored interrupt controller

(NVIC) block with eight interrupt inputs and also includes a

Wakeup Interrupt Controller (WIC). The WIC can wake the

processor from Deep Sleep mode, allowing power to be switched

off to the main processor when the chip is in Deep Sleep mode.

The CPU subsystem includes an 8-channel DMA engine and

also includes a debug interface, the serial wire debug (SWD)

interface, which is a two-wire form of JTAG. The debug configu-

ration used for PSoC 4100S Plus has four breakpoint (address)

comparators and two watchpoint (data) comparators.

Flash

The PSoC 4100S Plus device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The low-power flash block is

designed to deliver two wait-state (WS) access time at 48 MHz.

The flash accelerator delivers 85% of single-cycle SRAM access

performance on average.

SRAM

16 KB of SRAM are provided with zero wait-state access at

48 MHz.

SROM

An 8-KB supervisory ROM that contains boot and configuration

routines is provided.

System Resources

Power System

The power system is described in detail in the section Power. It

provides assurance that voltage levels are as required for each

respective mode and either delays mode entry (for example, on

power-on reset (POR)) until voltage levels are as required for

proper functionality, or generates resets (for example, on

brown-out detection). PSoC 4100S Plus operates with a single

external supply over the range of either 1.8 V ±5% (externally

regulated) or 1.8 to 5.5 V (internally regulated) and has three

different power modes, transitions between which are managed

by the power system. PSoC 4100S Plus provides Active, Sleep,

and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU

subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep

mode, while all peripherals and interrupts are active with

instantaneous wake-up on a wake-up event. In Deep Sleep

mode, the high-speed clock and associated circuitry is switched

off; wake-up from this mode takes 35 µs. The opamps can

remain operational in Deep Sleep mode.

Clock System

The PSoC 4100S Plus clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that there are no metastable conditions.

The clock system for the PSoC 4100S Plus consists of the IMO,

ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz ECO and

PLL, and provision for an external clock. The WCO block allows

locking the IMO to the 32-kHz oscillator.

Figure 3. PSoC 4100S Plus MCU Clocking Architecture

The HFCLK signal can be divided down as shown to generate

synchronous clocks for the Analog and Digital peripherals. There

are 18 clock dividers for the PSoC 4100S Plus (six with fractional

divide capability, twelve with integer divide only). The twelve

16-bit integer divide capability allows a lot of flexibility in

generating fine-grained frequency. In addition, there are five

16-bit fractional dividers and one 24-bit fractional divider.

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4100S Plus. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it

can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO

tolerance with Cypress-provided calibration settings is ±2% over

the entire voltage and temperature range.

ILO Clock Source

The ILO is a very low power, nominally 40-kHz oscillator, which

is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven

counters can be calibrated to the IMO to improve accuracy.

Cypress provides a software component, which does the

calibration.

P e rip h e ra l

D ividers

A nalog

D ivider

clk_ sys

P re sca le r

clk_ h f

Pe riphera l C locks

S A R Clo ck

EC O

IM O

WC O

IL O

clk_e xt

clk_ lf

P LL

Divide By

2,4,8

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