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PSoC® 4: PSoC 4100S Plus

Datasheet

Document Number: 002-19966 Rev. *F

Page 14 of 42

Power

The following power system diagram shows the set of power

supply pins as implemented for the PSoC 4100S Plus. The

system has one regulator in Active mode for the digital circuitry.

There is no analog regulator; the analog circuits run directly from

the VDD input.

Figure 5. Power Supply Connections

There are two distinct modes of operation. In Mode 1, the supply

voltage range is 1.8 V to 5.5 V (unregulated externally; internal

regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Mode 1: 1.8 V to 5.5 V External Supply

In this mode, PSoC 4100S Plus is powered by an external power

supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of PSoC 4100S Plus supplies the internal logic and its

output is connected to the VCCD pin. The VCCD pin must be

bypassed to ground via an external capacitor (0.1 µF; X5R

ceramic or better) and must not be connected to anything else.

Mode 2: 1.8 V ±5% External Supply

In this mode, PSoC 4100S Plus is powered by an external power

supply that must be within the range of 1.71 to 1.89 V; note that

this range needs to include the power supply ripple too. In this

mode, the VDD and VCCD pins are shorted together and

bypassed. The internal regulator can be disabled in the firmware.

Bypass capacitors must be used from VDDD to ground. The

typical practice for systems in this frequency range is to use a

capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

An example of a bypass scheme is shown in the following

diagram.

Figure 6. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Analog

Domain

VDDA

VSSA

VDDA

1.8 Volt

Regulator

Digital

Domain

VDDD

VSSD

VDDD

VCCD

VDDD

VSS

1.8 V to 5.5 V

0.1

F

VCCD

0.1

F

Power supply bypass connections example

F

1.8 V to 5.5 V

0.1

F

VDDA

PSoC 4100S Plus

µF

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