Document Number: 002-19966 Rev. *F

Page 12 of 42

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Alternate Pin Functions

Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin

assignments are shown in the following table. Note that this is preliminary and subject to change.

Port/Pin

Analog

Smart I/O

ACT #0

ACT #1

ACT #3

DS #2

DS #3

P0.0

lpcomp.in_p[0]

tcpwm.tr_in[0]

scb[2].uart_cts:0

scb[2].i2c_scl:0

scb[0].spi_select1:0

P0.1

lpcomp.in_n[0]

tcpwm.tr_in[1]

scb[2].uart_rts:0

scb[2].i2c_sda:0

scb[0].spi_select2:0

P0.2

lpcomp.in_p[1]

scb[0].spi_select3:0

P0.3

lpcomp.in_n[1]

scb[2].spi_select0:1

P0.4

wco.wco_in

scb[1].uart_rx:0

scb[2].uart_rx:0

scb[1].i2c_scl:0

scb[1].spi_mosi:1

P0.5

wco.wco_out

scb[1].uart_tx:0

scb[2].uart_tx:0

scb[1].i2c_sda:0

scb[1].spi_miso:1

P0.6

exco.eco_in

srss.ext_clk:0

scb[1].uart_cts:0

scb[2].uart_tx:1

scb[1].spi_clk:1

P0.7

exco.eco_out

tcpwm.line[0]:3

scb[1].uart_rts:0

scb[1].spi_select0:1

P5.0

tcpwm.line[4]:2

scb[2].uart_rx:1

scb[2].i2c_scl:1

scb[2].spi_mosi:0

P5.1

tcpwm.line_compl[4]:2

scb[2].uart_tx:2

scb[2].i2c_sda:1

scb[2].spi_miso:0

P5.2

tcpwm.line[5]:2

scb[2].uart_cts:1

lpcomp.comp[0]:2

scb[2].spi_clk:0

P5.3

tcpwm.line_compl[5]:2

scb[2].uart_rts:1

lpcomp.comp[1]:0

scb[2].spi_select0:0

P5.4

tcpwm.line[6]:2

scb[2].spi_select1:0

P5.5

tcpwm.line_compl[6]:2

scb[2].spi_select2:0

P1.0

ctb0_oa0+

SmartIo[2].io[0]

tcpwm.line[2]:1

scb[0].uart_rx:1

scb[0].i2c_scl:0

scb[0].spi_mosi:1

P1.1

ctb0_oa0-

SmartIo[2].io[1]

tcpwm.line_compl[2]:1 scb[0].uart_tx:1

scb[0].i2c_sda:0

scb[0].spi_miso:1

P1.2

ctb0_oa0_out

SmartIo[2].io[2]

tcpwm.line[3]:1

scb[0].uart_cts:1

tcpwm.tr_in[2]

scb[2].i2c_scl:2

scb[0].spi_clk:1

P1.3

ctb0_oa1_out

SmartIo[2].io[3]

tcpwm.line_compl[3]:1 scb[0].uart_rts:1

tcpwm.tr_in[3]

scb[2].i2c_sda:2

scb[0].spi_select0:1

P1.4

ctb0_oa1-

SmartIo[2].io[4]

tcpwm.line[6]:1

scb[3].i2c_scl:0

scb[0].spi_select1:1

P1.5

ctb0_oa1+

SmartIo[2].io[5]

tcpwm.line_compl[6]:1

scb[3].i2c_sda:0

scb[0].spi_select2:1

P1.6

ctb0_oa0+

SmartIo[2].io[6]

tcpwm.line[7]:1

scb[0].spi_select3:1

P1.7

ctb0_oa1+

sar_ext_vref0

sar_ext_vref1

SmartIo[2].io[7]

tcpwm.line_compl[7]:1

scb[2].spi_clk:1

P2.0

sarmux[0]

SmartIo[0].io[0]

tcpwm.line[4]:0

csd.comp

tcpwm.tr_in[4]

scb[1].i2c_scl:1

scb[1].spi_mosi:2

P2.1

sarmux[1]

SmartIo[0].io[1]

tcpwm.line_compl[4]:0

tcpwm.tr_in[5]

scb[1].i2c_sda:1

scb[1].spi_miso:2

P2.2

sarmux[2]

SmartIo[0].io[2]

tcpwm.line[5]:1

scb[1].spi_clk:2

P2.3

sarmux[3]

SmartIo[0].io[3]

tcpwm.line_compl[5]:1

scb[1].spi_select0:2