ATSAMB11XR datasheet(67/87 Pages) MICROCHIP

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13.

ATSAMB11-XR2100A Design Considerations

The ATSAMB11-XR2100A is offered in a shielded Land Grid Array (LGA) package with organic laminate

substrates. The LGA package makes the second level interconnect (from package to the customer PCB)

with an array of solderable surfaces. This may consist of a layout similar to a BGA with no solder spheres.

However, it may also have an arbitrary arrangement of solderable surfaces that typically includes large

planes for grounding or thermal dissipation, smaller lands for signals or shielding grounds, and in some

cases, mechanical reinforcement features for mechanical durability.

13.1

Layout Recommendation

Referring to the SiP footprint dimensions in Figure 11-1, it is recommended to use solder mask defined

with PCB pads 0.22 mm wide that have a 0.4 mm pitch. A Sample PCB pad layout in following figure

shows the required vias for the center ground paddle.

Figure 13-1. PCB Footprint For ATSAMB11-XR2100A

The land design on the customer PCB should follow the following rules:

The solderable area on the customer PCB should match the nominal solderable area on the LGA

package 1:1.

The solderable area should be finished with organic surface protectant (OSP), NiAu, or a solder

cladding.

The decision on whether to have a solder mask defined (SMD) land or a non-solder mask defined

(NSMD) land depends on the application space.

–

SMD: If field reliability is at risk due to impact failures such as dropping a hand-held portable

application, then the SMD land is recommended to optimize mechanical durability.

–

NSMD: If field reliability is at risk due to a solder fatigue failure (temperature cycle related

open circuits), then the NSMD land is recommended to maximize solder joint life.

13.1.1

Power and Ground

Proper grounding is essential for correct operation of the SiP and peak performance. Figure 11-1 shows

the bottom view of the ATSAMB11-XR2100A SiP with exposed ground pads. The SiP exposed ground

pads must be soldered to customer PCB ground plane. A solid inner layer ground plane should be

provided. The center ground paddle of the SiP must have a grid of ground vias solidly connecting the pad

to the inner layer ground plane (one via per exposed center ground pads J41 to J49).

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 67

ATSAMB11XR датащи(PDF) 67 Page - Microchip Technology