| поискавой системы для электроныых деталей |
|
ATSAMB11XR датащи(PDF) 25 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
ATSAMB11XR датащи(HTML) 25 Page - Microchip Technology |
|
25 / 87 page ![]() 7.1.1 Features The processor features and benefits are: • Tight integration with the system peripherals to reduce area and development costs • Thumb instruction set combines high code density with 32-bit performance • Integrated sleep modes using a Wakeup Interrupt Controller for low power consumption • Deterministic and high-performance interrupt handling via Nested Vector Interrupt Controller for time-critical applications • Serial Wire Debug reduces the number of pins required for debugging • DMA engine for Peripheral-to-Memory, Memory-to-Memory, and Memory-to-Peripheral operation 7.1.2 Wakeup Sources Ultra_Low_Power is the lowest possible power state for the system. In Ultra_Low_Power state, ARM Cortex-M0, BLE core, GPIO's, and all other peripheral cores are powered-down. Only AON-GPIO_0 and AON-Sleep timer are functional in this state. ATSAMB11 contains the following wake-up sources that wake up the system from Ultra_Low_Power mode: • BLE events • AON-GPIO_0 • AON-Sleep timer 7.1.3 ARM Module Descriptions 7.1.3.1 Timer The 32-bit timer block allows the CPU to generate a time tick at a programmed interval. This feature can be used for a wide variety of functions such as counting, interrupt generation, and time tracking. Note: ARM Timer is one of the reserved resources being used by the BLE stack. Application must refrain from using this peripheral. 7.1.3.2 Dual Timer The APB dual-input timer module is an APB slave module consisting of two programmable 32-bit down- counters that can generate interrupts when they expire. The timer can be used in a Free-running, Periodic, or One-shot mode. 7.1.3.3 Watchdog Timer The two watchdog blocks allow the CPU to be interrupted, if it has not interacted with the watchdog timer before it expires. In addition, this interrupt will be an output of the core, so that it can be used to reset the CPU in the event that a direct interrupt to the CPU is not useful. This will allow the CPU to get back to a known state in the event, a program is no longer executing as expected. The watchdog module applies a reset to a system in the event of a software failure, providing a way to recover from software crashes. Watchdog timer 0 is a reserved resource, being used by the BLE stack. Application must refrain from using the watchdog timer 0. 7.1.3.4 Always-On (AON) sleep Timer This timer is a 32-bit countdown timer that operates on the 32 kHz sleep clock. It can be used as a general-purpose timer for the ARM or as a wake-up source for the chip. It has the ability to be a one-time programmable timer, as it will generate an interrupt/wake-up on expiration and stop operation. It also has the ability to be programmed in an auto reload fashion, where it will generate an interrupt/wake-up and then proceed to start another countdown sequence. ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 25 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |