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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATSAMB11XR датащи(PDF) 56 Page - Microchip Technology |
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ATSAMB11XR датащи(HTML) 56 Page - Microchip Technology |
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56 / 87 page  Table 10-10. SPI Slave Timing Parameters (1) Parameter Symbol Min. Max. Units Clock Input Frequency (2) fSCK 2 MHz Clock Low Pulse Width tWL 55 ns Clock High Pulse Width tWH 55 Clock Rise Time tLH 0 7 Clock Fall Time tHL 0 7 TXD Output Delay(3) tODLY 7 28 RXD Input Setup Time tISU 5 RXD Input Hold Time tIHD 10 SSN Input Setup Time tSUSSN 5 SSN Input Hold Time tHDSSN 10 Note: 1. Timing is applicable to all SPI modes. 2. Maximum clock frequency specified is limited by the SPI Slave interface internal design. Actual maximum clock frequency can be lower and depends on the specific PCB layout. 3. Timing based on 15 pF output loading. 10.9.3 SPI Master Timing The SPI Master Timing is provided in the following figure and table. ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 56 |
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